AMD: R9xx Speculation

Discussion in 'Architecture and Products' started by Lukfi, Oct 5, 2009.

  1. neliz

    neliz GIGABYTE Man
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    Please, keep silent, you're not adding anything to this topic except some complete B*S*
     
  2. UniversalTruth

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    Have you seen this:



    http://semiaccurate.com/forums/showthread.php?p=71680#post71680
    :lol:


    Perhaps Charlie is doing the same- adding some..... :shocked:
     
  3. CarstenS

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    Interesting.
    Gone are the days of 3-way or Quad-CrossfireX in the HDx8xx line of products? Or is the single-chip high-end really moved up to the HDx9xx range?


    BTW:
    Tessellation Unit is still singular. So either left at it's current state or they significantly beefed it up, but from the wording it seems highly unlikely that they've taken the distributed approach Nvidia is so proud of.
     
  4. neliz

    neliz GIGABYTE Man
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    Charlie is FAR more correct than you have been so far.
     
  5. UniversalTruth

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    You don't respect my opinion, do you? I don't care who is more correct and who is not. Because all people are equal under the NDA. :roll:
     
  6. Kaotik

    Kaotik Drunk Member
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    Well wasn't it the common understanding that it was triangle setup/rasterization that was holding the tesselator back anyway?
     
  7. Jawed

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    Other new stuff: UVD 3, AMD HD3D and HDMI 1.4a.

    Compelling stuff.
     
  8. Robert Varga

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    Isn't HDMI 1.4a needed for that Open3D? Nice, so it's here finally. LINK
     
  9. no-X

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    I'm quite curious about the mentioned "Image quality enhancement technology"

    UniversalTruth: I think members are trying to separate fake and real leaks. It's not very helpfull to start speculations based on obvious fakes...
     
  10. Sontin

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    No, the limitation is in the front-end. Juniper and Cypress are able of one tri/clock. But the front-end is to slow to produce this triangle with tessellation.
     
    #2330 Sontin, Sep 28, 2010
    Last edited by a moderator: Sep 28, 2010
  11. itsmydamnation

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    im sure there were plenty of situations found where cypress wasn't even hitting its 0.8 tri a clock under heavy tessellation.
     
  12. rpg.314

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    Interesting words, wonder what they mean.
     
  13. Jawed

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    I think tessellation was made slow because setup/rasterisation is the bottleneck. It's literally pointless producing small triangles faster, because they'll just fill a queue, which then grinds to a halt.

    In other words, without fine-grained setup and rasterisation, increased-tessellation throughput offers no gain.
     
  14. yuri

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    Hi there :) I'm wondering if there is a connection with this:
    Source: the official AMD Fusion blog
     
  15. PSU-failure

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    Well, GF100's tessellation approach is quite brute force...

    While Evergreen is slow, it seems to be connected to something else than the tessellator itself or even the rasterizer/setup throughput.
     
  16. Kaotik

    Kaotik Drunk Member
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    The 3D games part of "HD3D" is already supported on all HD-series Radeons AFAIK?
    (Since Cat 10.3)

    Transcoding works on any HD-series card, it uses stream processors, not UVD
     
  17. OlegSH

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    It's quite elegant considering slide below:
    [​IMG]
     
    #2337 OlegSH, Sep 28, 2010
    Last edited by a moderator: Sep 28, 2010
  18. Sontin

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    Do you have a link to the presentation?
     
  19. OlegSH

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    Nope
     
  20. gongo

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    Barts XT should not be in the 6800 class, that would be epic failure on AMD part....i know its just business but.... the lowest goal i can accept is to call it 6790 and go for 239 bucks. Talk about GPU sloooowdown...

    BTW will the HD6 series output audio and video streams separately from the connectors? It is a bit silly to always on ma AVR just to get to ma desktop with HD audio.
     
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