Upon further review, I agree that I mixed up the signaling rates for the standard. I may have conflated the transition for the first and second WideIO memory standards, which does go from SDR to DDR.
The variations may be something the standard as it is would not see as being separable.
A slide from Hynix seemed to apply a distinction between HBM1 and HBM2 where 1 was 1Gbps with a granularity of 32B, while 2 was 2Gbps with a granularity of 64B.
Perhaps this fits in with pseudo channel mode where Hynix chose to increment capacity, bandwidth, and burst length at the same time.
I think pseudo channel works by using the same bank twice, by mapping a logical bank such that a physical bank has half its columns mapped to one or the other bank. An activation would appear to activate two half-pages. There would be twice as many pages since HBM2 starts at double the capacity, so the pages have somewhere to stretch to.
A burst length of 4 doesn't need two successive cycles with column addresses like BL2, since the address corresponding to the first half of the burst implicitly carries over to the other half.
However, what if the setup was tweaked so that something was supplied between two successive bursts, giving a column address corresponding to the other pseudo-channel?
(edit: possible error, the banks are physically split into sub-banks, so this may be feeding the additional address into the other sub-bank, which would be more flexible than the same page)
Legacy mode would keep to the standard, whereas the tweaked HBM2 module and a suitably updated controller would perform a little outside math and fill in a cycle on the column address bus that wouldn't normally be considered necessary.
It may be that the lower capacity HBM1 modules do not supply enough bits from their arrays to heavily tax the interface before running into their own timing constraints, so it's DDR that decides to run half as fast.
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