AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

There was an earlier HBM vs GDDR5 comparison that was similar to this.
The change seems to be that this says HBM2, and the bandwidth and power gains are more modest versus GDDR5. Perhaps this is relative to the most recent variations of both. The density section starts a 16Gb per stack rather than 8.
Other than that, I am curious what the generational change would be between the generations. There was an originally projected higher ceiling for the data rate past Gen1, which this doesn't seem to promise.
 
The base die apparently is a bit larger, and I suppose they never specified what strength aspirin or what form they were comparing it to. 10mm diameter pills would be bigger.
It also comes in suppository form...
 
Hmm, never occurred to me that HBM was a JEDEC standard & NV would be using it too o_O
Things that happen when you tune out for a while :neutral:
 
Things that happen when you tune out for a while :neutral:
True! However, that Pascal would use stacked RAM has been "public knowledge" for quite some time. As I recall, this was the case even at the time Pascal didn't exist at all, and Volta was listed as the successor of Maxwell (and using stacked RAM...)
 
Good news AMD, the completely wrong diagram stuck in years' worth of ISA documentation is getting broadcast by tech sites.
 
The XNACK mask values would be restricted to Carizzo since they signal when a thread's memory translation has failed, which is useful for an APU whose GPU is intended to access system memory freely.
The special data source identifiers were reserved in the Sea Islands ISA doc, so I guess we can wonder aloud about other reserved values and what those could become.
 
Good news AMD, the completely wrong diagram stuck in years' worth of ISA documentation is getting broadcast by tech sites.


As many of peoples who read this type of articles will understand anything at what they see in this diagram.. you overestimate the knowledge of peoples who visit thoses sites..

Seriously i will not understand why AMD will provide 6months ago a complete detail of their next architectures.. i think this documentation is more related to Tonga than anything else ( who should be considered in this documentation as GCN 3th release ( )
 
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Seriously i will not understand why AMD will provide 6months ago a complete detail of their next architectures.. i think this documentation is more related to Tonga than anything else ( who should be considered in this documentation as GCN 3th release ( )
Huh? Hasn't it been clear the whole time it's about Tonga aka "GCN 3" aka Volcanic Islands?
 
Huh? Hasn't it been clear the whole time it's about Tonga aka "GCN 3" aka Volcanic Islands?

Its seems for some it was not the case... ( not here, but when i read articles like that..) .. sorry was not directed at peoples on beyond, mostly on what i read on other forums / sites about this doc.
 
So frequencies would presumably be outside of FCC regulated spectrum or the range of the fields would be negligibly small? (TCI is an incredibly smart idea for both signal and power transmission.)
 
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So frequencies would presumably be outside of FCC regulated spectrum or the range of the fields would be negligibly small? (TCI is an incredibly smart idea for both signal and power transmission.)
It's both: it's based on magnetic instead of electrical fields, so it's a completely different animal, not related to the FCC regulated spectrum at all.. And the range of magnetic fields is incredibly small. In this particular case, the fields is so weak that the wafer needs to be thinned to a couple of microns.
 
I'm no professional EE but one induces the other and vice-versa; it does sound like the range is extremely small if extra thin wafers have to be used. Presumably the package is also shielded or takes care of any interference it creates into account in other ways.
 
I'm no professional EE but one induces the other and vice-versa; it does sound like the range is extremely small if extra thin wafers have to be used.
Yes, they are related: a magnetic field can be created by change in electrical charge (current), while an electric field gets created by an electrical charge. (potential.)

In turn, a changing magnetic field generates a current in a nearby inductor, while a changing electric field creates a changing voltage potential.
To measure them, you use very different detection circuits.

My transistor level thinking is rusty, but if you look at slide 14, you see that, on the RX side, the changes in magnetic field result in charge built up in the coil. Since the coil is connected to high impedant transistor gates, it creates a voltage difference. Those pulses are then fed into latch circuit, which convert the pulses into steady values. It's trivially simple.

For RF, you'd need some kind of resonant detection circuit to tune in to a very particular frequency, and, more importantly, tune out everything else. Much more complicated.

Presumably the package is also shielded or takes care of any interference it creates into account in other ways.
I don't think any shielding is needed. Just like you don't need shielding around your cell phone inductive charging station at home.

You'd only need it if you put your chip in a very strong magnetic field that happens to oscillate at a few GHz.
 
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