AMD: Navi Speculation, Rumours and Discussion [2019-2020]
- Thread starter Kaotik
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it doesn't work like that, you can't just keep bolting on CUs. There are other things to consider as the chip gets larger. Things like timing, synchronization, latency become an issue - all of this coupled with making sure thermally everything is going to work under pressure as well.
DegustatoR
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Around 1.5 GHz would be a much safer assumption.
Yep, that is the one.
D
Deleted member 13524
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I'm not sure AMD would clock it that low.
With 96 ROPs, it would make it have a much lower fillrate per compute throughput than any Navi card so far.
Frenetic Pony
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MS Confirming "12 teraflops" for Xsx: https://www.engadget.com/2020/02/24...gn=homepage&utm_medium=internal&utm_source=dl
Meaning, since it's semi-custom only, we've pretty much guaranteed got a 48CU part for upper mid range RDNA2 coming, and the XSX has it (cut down a bit? who knows). Not that such should be surprising, it's the same pattern of slow changes AMD likes and the 5500 chip already has that config per SE.
Meaning, since it's semi-custom only, we've pretty much guaranteed got a 48CU part for upper mid range RDNA2 coming, and the XSX has it (cut down a bit? who knows). Not that such should be surprising, it's the same pattern of slow changes AMD likes and the 5500 chip already has that config per SE.
No no no no no no no no no no.
Semi-custom APU chips CU counts have absolutely no relations whatsoever with PC GPUs CU counts. They can have just as many as they can fit there (and the architecture allows), or just as few as they want and everything in between (again with possible limitations from architecture dictating you need to have even number of CUs or something)
DavidGraham
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According to Jim from AdoredTV, the real reason for AMD constant use of high voltage on their GPUs is to protect cards from silicon degradation over the lifetime of the cards. NVIDIA is not affected by this because they have "exceptional" performance per watt.
Frenetic Pony
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They need the CU count to be stable for their arch, balanced with work distribution and bandwidth and etc. They are not going to develop an entire custom variant for a client and then not use that, the number line up almost perfectly for what they're going to do, and this is approximately what they did with the PS4 and Xbox One, which was just make somewhat custom variants of GPUs they already had.
Those previous two were just variants with things added on, XBOs Esram for example. Semi-custom very much does indicate about what consumer GPUs will be as an overall picture, just without the bells and whistles the clients want to add. EG we don't know if the 6700xt will have the PS5 (and doesn't the Xsx have it too?) fancy audio processing hardware, or etc. This goes doubly true today, with taping out chips on 7nm costing hundreds of millions of dollars, neither AMD nor MS want to spend however much of that it would cost just to add a few more CUs.
Of course they need to have balanced configurations, but no, they don't need to adhere to any specific discrete GPUs CU counts on any level and doing so wouldn't be any cheaper (relative of course, naturally it can be cheaper if the other option is bigger).
You need to design the APU layout from scratch anyhow, you can't copypasta discrete GPU in there, not even just the CU portion, so it's exactly the same to design it with whatever GPU configuration (the architecture allows) you want (again, of course making it bigger is more expensive, but not because it's not the same CU count)
Also AMD has made semi-custom solutions which have different CU counts compared to their discrete parts of same architecture, like 20 CU discrete Polaris and 24 CU Vega in an APU,
TL;DW but advanced techniques like boot-time calibration were implemented in Bristol Ridge and later in Polaris. The aim is to prevent overvolting of "fresh"/non-degraded chips not the way around.
Wow. They are basicly saying, that overvolting (which results in worse performance per watt) is needed because of problems, which are cause by bad performance per watt. Does it make any sense? I don't think so. In fact it would mean, that witnout overvolting, performance per watt would be better and with better performance per watt there would be no degradation issue. So, according to AdoredTV AMD is overvolting their producst to cure a problem caused by overvolting.
DavidGraham
Veteran
No, chip degradation is irrelevant to bad performance per watt, it forces them to increase voltages to prevent it from happening down the line.
The performance per watt thing comes into play only when questioning why NVIDIA doesn't need to raise voltage as much as AMD to protect against degradation, for which the answer is, their performance per watt is very good to to begin with (don't use high voltages) and thus don't need to raise voltages by the same amount.
DavidGraham
Veteran
Yes, but maybe this mitigates the problem a little, but doesn't solve it completely, hence the need for AMD GPUs to increase the voltages.
Is this a picture of a paper or physical display? Is this supposed to be a disclosure from Hynix?
It seems like an odd mix of topics in that pic (Hynix logo on a GPU spec table, some PCB-related writing, and financial tables in one spot).
If this is some kind of internal source at a manufacturer, would it be common practice to use a government certification number for AMD as a code name?
Including the Hynix logo seems weird if Hynix isn't intending to provide the memory speed listed for the board this year.
As far as the numbers in the table. The L2 seems large, but at 12MB it seems like it's not as clean a match to the 4096-bit bus. I don't know if there's anything specifically wrong with having 12MB, just that it's often multiples to 2 for slices and slice capacities throughout. Vega 20 has the same bus width and 4 MB total, which is probably subdivided into 16 slices internally. Navi 10 has that many slices as well, and gets to 4 MB total. 3/4 of a MB per slice seems a bit out of pattern (and not in the slice capacity range given in the RDNA whitepaper, for what it's worth).
The CU count doesn't seem inconsistent, assuming RDNA does relax some of the constraints in unit counts versus GCN.
I haven't found an entirely consistent set of ratios of CUs/WGPs versus shader engines and ROP count.
ROPs in particular stand out at 96. There has been a preference for powers of 2 for RBEs per shader engine in the past. For one thing, it does align pixel writes to preferred cache line granularities and AMD's documented recommendation that writes hit 256 Byte granularity if DCC is involved--and for the ROPs it would tend to be. 96 can be made to fit, if subdivided 6 ways, but then it doesn't symmetrically fit the CU count and it raises questions about screen tiling and some of the parameters for the rasterizers and front end logic.
I'm not sure if the word protect is being used in a different way than its main definition. Physical degradation of the silicon and board components is generally proportional to voltage, so it would get worse at higher voltages.
There is a need for a voltage margin to buffer transient spikes in demand and for product consistency in the face of device aging, but I'm not sure I'd characterize that as protecting the card as much as staying true to the specs.
Although it was claimed that the VBIOS settings for many of these features were not enabled in many products. Perhaps they were intended for specific use cases and AMD neglected to mention it, or they weren't as workable or effective as the marketing stated. It might explain why AMD advertised them as new features for more than one GPU launch if it wound up not using them effectively.
DavidGraham
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Then may be this is the real reason then? Upholding voltages to stay within spec and not degrade the product?
Rootax
Veteran
In any case, nvidia has to do the same thing I guess. If they "fine tune" it better, or need less overhead to stay in specs over time, it's leave another room for improvement for amd. The question is do they have the ressources (man power, money, time) to fix this kind of things.
DegustatoR
Legend
I'm pretty sure that laws of physics don't care about what AMD would or wouldn't do.
With Navi 10 hitting 235W running at about 1.8GHz there's exactly zero chances of a chip which will be twice as wide to hit 2.0 GHz while remaining under 300W of power consumption.
D
Deleted member 13524
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Seems a bit naive to assume RDNA2 will have the same power/frequency curves as RDNA1.
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