It might be the same as with Polaris and Vega. Navi will be for mid-range and low-end chips, ie. Polaris successor and post-Navi will arrive as Vega10/20 replacement, ie. large chip first. Maybe both will be GFX10, without big architecture differences, just different code names
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Err.. what? There's always new and faster architecture coming in a year or so
Ext3h
Regular
Going by how Navi is marketed so far, it's attributes are pretty much narrowed down:
- Behaves like GCN from application perspective, including performance characteristics
- Built from chiplets instead of monolithic die
- Dispatch / scheduling over Infinity Fabric
- Central IO / L3 cache die, same as in Zen 2, only L2 local
- Page-level dynamic on-demand replication / deduplication / migration, using memory controllers and L2 caches per die
- If page-level, possibly also the option to dynamically swap out via Infinity Fabric to host
- Possibly hybrid with 2-4 chiplets per IO-die, and dynamic replication between IO-dies
At the same time we are seeing the "next gen" hints. But contrary to Navi it's not marketed as a successor to the GCN legacy.
Possibly indicates breaking changes, which makes it not the obvious choice for consoles. Or maybe we have just reached the end of the roadmap.
Breaking changes in the ISA appear likely though, as the competition has successfully exceeded the performance limits of the Vega/Navi ISA.
For next-gen, I assume what we can expect are instructions / hardware dedicated to the "packed matrix multiplication" performance problem. Which does require adaption to the software to utilize it, so not a free upgrade.
We will most likely also see solutions to issues and bottlenecks which had been introduced by the "scale-able" design of Navi.
We must assume that Navi isn't going to scale properly in all aspects yet, and some limitations only surfaced during development and can't be corrected now without breaking the schedule.
Love_In_Rio
Veteran
Lately?. New architectures frequency is much more than a year.
DmitryKo
Veteran
There is a lot of confusion in regard to current AMD alphanumerical code names - it seems like people keep confusing GPU die codenames like Vega 10/20 and Polaris 10/20/30 with the product marketing names, like RX Vega 11 for integrated graphics in the various Ryzen APUs.
For all we know, Vega is a high end GCN5 HBM2 part: Vega 10 is a 14nm version and Vega 20 is a 7 nm version.
Polaris is a mid-range GCN4 GDDR5 part, Palaris 10 is a 14nm die, Polaris 20 is a 14 nm++ respin and Polaris 30 is a 12nm version.
Likewise Navi would be a mid-range GDDR6 part, Navi 10 is the initial 7 nm version and Navi 20 is the 7nm++ version. Not the "high-end Navi" - that would rather be the next-gen "Arcturus", a high-end HBM3 part.
So these should be treated like Vega 1.0/2.0, Polaris 1.0/2.0/3.0, etc. - different revisions of the same die.
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Dunno, the arch code name numbering was once described as a mere "hint of project start". Thus VEGA 20 project started after VEGA 10 project, etc.
As for console deals... Numerous ppl say the console makers want compatibility - the new gen has to be legacy/GCN based. This suits Navi perfectly. As for new arch coming shortly after GCN - PS3 was released a year before nV G80. So why not?
As for console deals... Numerous ppl say the console makers want compatibility - the new gen has to be legacy/GCN based. This suits Navi perfectly. As for new arch coming shortly after GCN - PS3 was released a year before nV G80. So why not?
Getting a product to market at the right time is far more important than holding out for a new architecture - something that most customers won't care about.
It depends on how the binaries are built and your emulation method that determines if you can't make compatibility happen.
We don't have those issues on PC because of the way abstraction is handled.
And we hope MS has their virtualization layer and driver layer's setup properly to be mostly immune to low-level instruction-set changes.
Tkumpathenurple
Veteran
Might there be scope for these super SIMD' with their pairings of ALU's to just function as a single ALU, as seen in GCN?
Sony's patents for BC seem to be focused on running the CPU/GPU at the clocks of the original hardware. If Navi does consist of super SIMD's, and these find their way into the next generation, I expect Sony will try to trick the software into thinking it's running on original hardware. Assuming that's possible, but I'm a simpleton, so I've no idea.
Maybe they'll get adventurous and trick the software into thinking it's running on overclocked hardware, given that there don't seem to have been any problems with "boost mode" for pre-Pro PS4 games.
Microsoft look to have a pretty easy road ahead of them, considering how they've been smashing it on the XBox BC front. But I'm sure even they would appreciate such an easy approach in hardware.
So, if both Sony and Microsoft are using Navi or beyond, and Navi is post GCN, how likely is it that an architectural change would render it difficult to run or easily emulate the GCN code of much lower clocked GPU's?
Sony's patents for BC seem to be focused on running the CPU/GPU at the clocks of the original hardware. If Navi does consist of super SIMD's, and these find their way into the next generation, I expect Sony will try to trick the software into thinking it's running on original hardware. Assuming that's possible, but I'm a simpleton, so I've no idea.
Maybe they'll get adventurous and trick the software into thinking it's running on overclocked hardware, given that there don't seem to have been any problems with "boost mode" for pre-Pro PS4 games.
Microsoft look to have a pretty easy road ahead of them, considering how they've been smashing it on the XBox BC front. But I'm sure even they would appreciate such an easy approach in hardware.
So, if both Sony and Microsoft are using Navi or beyond, and Navi is post GCN, how likely is it that an architectural change would render it difficult to run or easily emulate the GCN code of much lower clocked GPU's?
Navi is almost certainly GCN in every sense of it, they would have advertised it as next gen architecture or something for sure instead just saying it has nexgen memory (typo intended) if it wasn't.
And they've already said that 2020 will see new architecture (which could of course just be another GCN architecture but still it's more than they've said about Navi being somehow radically different)
Tkumpathenurple
Veteran
That's what all legit sources say, but I was basing what I said on the below.
https://wccftech.com/exclusive-first-amd-navi-gpu-will-have-40-cus-and-is-codenamed-navi-12/
Sorry, I should have been clear and linked it in my previous post, thereby establishing context
https://wccftech.com/exclusive-first-amd-navi-gpu-will-have-40-cus-and-is-codenamed-navi-12/
Sorry, I should have been clear and linked it in my previous post, thereby establishing context
That's what all legit sources say, but I was basing what I said on the below.
https://wccftech.com/exclusive-first-amd-navi-gpu-will-have-40-cus-and-is-codenamed-navi-12/
Sorry, I should have been clear and linked it in my previous post, thereby establishing context
This part alone is enough to show it's at least partly fake information
Like said already, there's no chance AMD would release "high end Navi" 2 years later after first Navi, especially when they already confirmed actual next gen for 2020
DmitryKo
Veteran
Could you please explain the logic behind your assumptions above?
AMD is not really 'marketing' Navi yet - there is very little official information coming. But for all I know, they said Navi is definitely NOT a multi-die/chiplet design but rather a traditional monolithic design, because multiple dies look like explicit multi-GPU which is not optimal for gaming applications (and Nvidia published several research papers on a multi-die architecture which behaves like a monolithic GPU to the OS).
WCCFtech currently assumes that Navi is a new 'post-GCN' architecture which is similar to the 'next gen'/Arcturus - even though they earlier assumed that Navi would be 'the last GCN' - and they're also standing by their claim that Navi 20 would be a high-end part, which makes no sense to me.
I think it's quite possible that Navi is the first post-GCN architecture - which either did not live up to expectations for multi-chip performance or was missing important new features like hardware-accelerated raytracing to become a flagship part (or it was never intended to be a flagship, just like Polaris never was). The reason why AMD would not advertise Navi as 'next-gen' could be their marketing department wants to associate 'next-gen' with a flagship part - not a mid-range part having Vega 56 performance at a lower price point.
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Love_In_Rio
Veteran
This has a lot of sense, ray tracing is the new buzzword nowaday and without it they wont call it next gen.
If we play the buzzword game, back in 2011 PhysX was at full strength. Still, AMD called GCN "next-gen", "new arch", flagship, etc. and released Tahiti with no problem.
DavidGraham
Veteran
PhysX wasn't standard, it wasn't part of DX. It was accelerated through CUDA. Ray Tracing is standard and is part of DX.
I think WCCFTech could get correct information, but interpreted it in a wrong way. E. g. the source could tell them, that Navi 20 will be the biggest die and their they interpreted, that biggest die = high-end part. It could be in fact successor of Vega 20 supporting high-speed FP64 and AI features. Such product could be released event at the end of 2020 at the same time as the "next-gen". First "next-gen" products could be gaming-focused, while last Navi products could be AI/HPC-focused.
DmitryKo
Veteran
I guess WCCFTech came to this conclusion on their own, probably on the assumption that "higher number" = "bigger die".
BTW it looks like they way AMD changed their engineering codenames with Arctic Islands is more straightforward than it used to be - where they would previously assign a new codename for each new die, even when it was a minor revision, and tag them with GFX6-GFX9 and GCN1-GCN5 to explain their generation, their current naming system seems to be based on three distinct parts:
architecture generation (Polaris, Vega, Navi),
die revision (1, 2, 3 etc),
scale factor (0, 1, 2 etc) : 0=full, 1=half, 2=quarter etc (scale down by TFLOPs/CUs??? or transistors/die size???)
For example:
Polaris 10 (Ellesmere) (232 mm² 5.7B) (2048:128:32) = 14 nm mid-range RX 470/480 (2016-06);
Polaris 11 (Baffin) (123 mm² 3B) (1024:64:16) = low-end RX 460/560 (2016-08);
Polaris 12 (Lexa) (101 mm² 2.2B) (512:32:16) = low-end 540/550 (2017-4);
Polaris 20 (Ellesmere XL/XT) = 14nm++ RX570/580 (2017-04);
Polaris 21 (Baffin) (1024:64:16) = 14nm++ RX 560 (2017-05);
Polaris 22 (1280 80:32) = 14nm++ RX Vega M Gx (Intel Core 8800G) (2018-01);
Polaris 30 = 12nm RX 590 (2018-11);.
Vega 10 (Greenland) (486 mm² 12.9B) (4096:224:64) = 14 nm top-end RX Vega 56/64 (2017-08);
Vega 12 (~120 mm² ~3B) (1024: ?: ?) = low-end Radeon Pro Vega 16/20 (Apple iMac Pro) (2017-11);
Vega 20 = 7 nm Radeon Instinct MI50/60 (2018-11).
The same logic would apply to Navi codenames:
Navi 10 = 7nm full-scale mid-range part; Navi 11/12/14 = scaled-down dies;
Navi 20 = revision/respin of Navi 10; Navi 21/22 etc. = revisions/respins of scaled-down dies.
For comparison, a list of known codenames starting with GCN:
PS. Never mind, Polaris 22 breaks the proposed system... these are probably just sequential numbers on the release timeline - not die revisions or scale factors.
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The thing is, next-gen after Navi is promised already for 2020 which leaves little room for 7nm+ EUV "shrink" of the original Navis. I don't see any reason to think there would be Navi 20, unless there will be separate HPC-version again
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