Assuming they continue the same pattern as with Zen 4/4c it's logical - Zen 5c CCD would have relatively less cache and thus benefits more from smaller node.https://www.techpowerup.com/319241/amd-zen-5c-ccds-made-on-more-advanced-3-nm-node-than-zen-5
AMD is reportedly building its upcoming "Zen 5" and "Zen 5c" CPU Core Dies (CCDs) on two different foundry nodes, a report by Chinese publication UDN, claims. The Zen 5 CCD powering the upcoming Ryzen "Granite Ridge" desktop processors, "Fire Range" mobile processors, and EPYC "Turin" server processors, will be reportedly built on the 4 nm EUV foundry node, a slightly more advanced node than the current 5 nm EUV the company is building "Zen 4" CCDs on. The "Zen 5c" CCD, or the chiplet with purely "Zen 5c" cores in a high density configuration; on the other hand, will be built on an even more advanced 3 nm EUV foundry node, the report says. Both CCDs will go into mass production in Q2-2024, with product launches expected across the second half of the year.
SRAM stops scaling at around 3-5nm class. TSMCs original N3B had still some scaling left in it, but the process overall had apparently some issues since TSMC has replaced it already with N3E which has exact same SRAM size as their N5 had
(Also we should all just stop talking about nanometers since they're literally just made up based on nothing. Last bit of relations "nanometers" had with the actual process size ended when we moved to FinFETs)