Cache is not memory? He speaks about "effective bandwidth no external bandwidth. I don't think somebody at EPIC expect GPU external bandwidth to grow anywhere close to 4GB/s that's between 20 and 40 more than what possible now. Even for internal bandwidth it will be a tough figure to reach, even with better architecture it would imply a consistent bump in clock speed.http://graphics.cs.williams.edu/archive/SweeneyHPG2009/TimHPG2009.pdf
The last slide clearly says that he is talking about memory bandwidth.
Anyway, RV870 has 1 Terabyte/s bw for texture fetch and 435 Gb/s bw from L1 to L2 cache.
I find the 1TB/s in the B3D own review too:
54GB/s is a lot if you consider the clock speed, last Intel architecture seems to provide 50GB/s read and write it seems it can peak @~100GB/s (from here). I don't know if it can read and write at the same time (it's a bit over my head) and it's likely a best case scenario. That's for 3.2GHz part.B3D said:This L1 is fully associative, and we're told it uses 256 bit cachelines, maintaining a cacheline size tradition that was started with the R300. You'll probably see a cute 1 TB/s fetch rate being quoted for the L1, but keep in mind that's aggregate, a sampler can only fetch from the L1 at a rate of ~54.4GB/s, and aggregate doesn't make much sense here since one sampler can't exactly fetch from another's L1.
For RV8xx it's read only.
But more educated members could shime in in this regard