It's a subject of some debate on places like r/emulation. The Altera Cyclone V SE FPGA SoC on the MiSTer has 110,000 configurable logic elements.
To put that into perspective, the Atari ST core implements a fully functional 68000 CPU using 5,100 of those elements.
It was a long held notion that hosting the Sega Saturn's six ASICs probably wouldn't be possible in the Cyclone V, until someone went ahead and made a Saturn core anyway. Currently in beta.
The MiSTer is nice because it's a relatively inexpensive way to get a pretty powerful FPGA. But it certainly has a theoretical upper limit.
There are way more advanced FPGAs available these days so there's room to grow for a possible future MiSTer 2.
