A completely open RISC ISA to rival ARM, x86

Discussion in 'PC Industry' started by fellix, Aug 22, 2014.

  1. fellix

    fellix Hey, You!
    Veteran

    Joined:
    Dec 4, 2004
    Messages:
    3,486
    Likes Received:
    397
    Location:
    Varna, Bulgaria
    New RISC-V architecture hopes to battle ARM and x86 by being totally open source
    :???:
     
  2. rpg.314

    Veteran

    Joined:
    Jul 21, 2008
    Messages:
    4,298
    Likes Received:
    0
    Location:
    /
    I don't see any vector extensions.

    So much for the extensibility to cloud computing. :(
     
  3. fuboi

    Newcomer

    Joined:
    Aug 6, 2011
    Messages:
    90
    Likes Received:
    45
    There are vector extensions, variable width. In fact some DARPA sponsored ASICs were focusing on that. If I'm not mistaking this ISA with another ISA, they're dime a dozen. Seemed to be a research focused ISA for students to play with. "Challenging ARM and x86" is some doped up shit, as if ISA technical merits had any kind of relevance for ARM or (triple lol) x86.
     
  4. Narishma

    Newcomer

    Joined:
    Mar 26, 2013
    Messages:
    3
    Likes Received:
    0
    You didn't look hard enough.
     
  5. Exophase

    Veteran

    Joined:
    Mar 25, 2010
    Messages:
    2,406
    Likes Received:
    429
    Location:
    Cleveland, OH
    Okay, so where are these vector extensions in the actual RISC-V spec?

    There's a section for SIMD but it's little more than a placeholder. And they don't seem that interested in it:

    They have integrated a vector coprocessor with the Rocket processor called Hwacha. But it's not merely an extension to Rocket's ISA, but a separate coprocessor. It's much more tightly coupled than a GPU would be, but not tightly coupled enough to be considered an ISA extension for the CPU. http://prism.sejong.ac.kr/download/PRISM2_download/3_AlbertOu_paper.pdf
     
  6. rpg.314

    Veteran

    Joined:
    Jul 21, 2008
    Messages:
    4,298
    Likes Received:
    0
    Location:
    /
    You might be right.

    Since you seemingly did, care to post a link or two?
     
  7. 3dilettante

    Legend Alpha

    Joined:
    Sep 15, 2003
    Messages:
    8,122
    Likes Received:
    2,873
    Location:
    Well within 3d
    The base ISA is certainly svelt.
    As an educational tool, it looks to be useful.

    Perhaps it is an argument for old-style RISC simplicity, or maybe a constraint inherent to the claim that it is not patent encumbered, but it has a retro just past the 20 year limit vibe to me.
    Memory handling, threading, security, virtualization, reliability, and synchronization of all sorts are a highly researched and also patented area, but the PDF is sparse.
    Simplicity can help for some of these issues, and maybe the extension mechanism would help. It's a lot to extend, though.
    Some of the points like fixing such ISA flaws as dated as Alpha's lack of byte loads and delay slots in MIPS are nice, but not issues of the cutting edge. I'm mulling over some of the responses to what possible shortfalls they introduced instead of the former problems.

    I'm hoping to read more details as far as other architectural considerations like memory model and some details on implementations, such as that vector coprocessor.
    I've been mulling over the future direction of computation these days, and I'm not sure about the totality of the projected path for RISC-V. There seems to be a niche or two both outside and within the three points made up of tiny networked processors, a personally held device, and massive warehouse data center.
     
Loading...

Share This Page

  • About Us

    Beyond3D has been around for over a decade and prides itself on being the best place on the web for in-depth, technically-driven discussion and analysis of 3D graphics hardware. If you love pixels and transistors, you've come to the right place!

    Beyond3D is proudly published by GPU Tools Ltd.
Loading...