A completely open RISC ISA to rival ARM, x86

[fellix]

New RISC-V architecture hopes to battle ARM and x86 by being totally open source

One of the pioneers of the original RISC instruction set has returned to the design table with a goal that’s nothing short of massive. David Patterson wants to reinvent computing with a completely open ISA, and he’s hoping that the time is right to finally blow the doors off the CPU industry — this time, by advocating for the adoption of the completely open ISA, RISC-V.

There are already a variety of open ISAs, but Patterson is hoping RISC-V will spark interest and uptake where other projects have sputtered. It’s hard to argue with the man’s credentials — he’s one of the original inventors of the RISC concept — but some of his critiques of the problems he wants RISC-V to solve ring truer than others.

RISC-V is designed for ultra-compact code sizes, allows for quadruple precision (128-bit floating point values) and can allow for 128-bit memory addressing — though it’s utterly impractical to think this will be needed in the short term. The whitepaper points out, however, that address size limitations is one mistake an ISA makes that’s hard to recover from — RISC-V’s 128-bit limit should serve us for the next 40-50 years.

 

[rpg.314]

I don't see any vector extensions.

So much for the extensibility to cloud computing.

 

[fuboi]

I don't see any vector extensions.

So much for the extensibility to cloud computing.

There are vector extensions, variable width. In fact some DARPA sponsored ASICs were focusing on that. If I'm not mistaking this ISA with another ISA, they're dime a dozen. Seemed to be a research focused ISA for students to play with. "Challenging ARM and x86" is some doped up shit, as if ISA technical merits had any kind of relevance for ARM or (triple lol) x86.

 

[Narishma]

I don't see any vector extensions.

So much for the extensibility to cloud computing.

You didn't look hard enough.

 

[Exophase]

Okay, so where are these vector extensions in the actual RISC-V spec?

There's a section for SIMD but it's little more than a placeholder. And they don't seem that interested in it:

In our opinion, packed-SIMD designs represent a reasonable design point when reusing existing wide datapath resources, but if significant additional resources are to be devoted to data-parallel execution then designs based on traditional vector architectures are a better choice.

They have integrated a vector coprocessor with the Rocket processor called Hwacha. But it's not merely an extension to Rocket's ISA, but a separate coprocessor. It's much more tightly coupled than a GPU would be, but not tightly coupled enough to be considered an ISA extension for the CPU. http://prism.sejong.ac.kr/download/PRISM2_download/3_AlbertOu_paper.pdf

 

[rpg.314]

You didn't look hard enough.

You might be right.

Since you seemingly did, care to post a link or two?

 

[3dilettante]

The base ISA is certainly svelt.
As an educational tool, it looks to be useful.

Perhaps it is an argument for old-style RISC simplicity, or maybe a constraint inherent to the claim that it is not patent encumbered, but it has a retro just past the 20 year limit vibe to me.
Memory handling, threading, security, virtualization, reliability, and synchronization of all sorts are a highly researched and also patented area, but the PDF is sparse.
Simplicity can help for some of these issues, and maybe the extension mechanism would help. It's a lot to extend, though.
Some of the points like fixing such ISA flaws as dated as Alpha's lack of byte loads and delay slots in MIPS are nice, but not issues of the cutting edge. I'm mulling over some of the responses to what possible shortfalls they introduced instead of the former problems.

I'm hoping to read more details as far as other architectural considerations like memory model and some details on implementations, such as that vector coprocessor.
I've been mulling over the future direction of computation these days, and I'm not sure about the totality of the projected path for RISC-V. There seems to be a niche or two both outside and within the three points made up of tiny networked processors, a personally held device, and massive warehouse data center.

 

[Deleted member 2197]

Examining the Top Five Fallacies About RISC-V​

In a little over a decade, RISC-V has arguably become at least the third most important instruction set architecture (ISA) for future applications of computing. In the next few years, it may become just as surprising to pick a proprietary ISA over the open RISC-V for a new project as it would be to pick a closed alternative to Ethernet or USB.

My colleagues at UC Berkeley and I predict that by the end of this decade, the dominant ISA for future product development will be the open RISC-V architecture. Companies around the world are already designing with RISC-V and the momentum is rapidly increasing, so this is a good time for the industry to take a closer look at RISC-V and examine some fallacies about it.

https://www.eetimes.com/examining-the-top-five-fallacies-about-risc-v/

 

[WhiningKhan]

Ah, David Patterson. I see his and Hennessy's book on computer architecture has, rather unsurprisingly, been renovated towards RISC-V instead of MIPS as it was back in the day. Haven't looked at RISC-V at all really but I've always assumed it to be quite MIPSy.

 

[Gubbi]

Arm v8 looks a lot more like mips as well, with 32 (31) registers, losing the implicit rotates, etc.

At least they didn't copy the branch delay slot

Cheers

 

[Laurent06]

Examining the Top Five Fallacies About RISC-V​

https://www.eetimes.com/examining-the-top-five-fallacies-about-risc-v/

Directly from one of founders of RISC-V, that surely is not biased.
As I would not be biased talking about why AArch64 is so much better than RISC-V ISA