Hello,
Jon Stokes form Ars Technica has recently summarized and simplified an article from realworld tech about 3d stacking.
If you are a technical guy - realworldtech
article
If you are from ' the wider audience' - here is the Ars Technica
article
So what are you thoughts on this topic? Is it only going to be limited to homogenous solutions, or will it extend to hetero ones?
I think the easiest stacking would be heterogenous, with one layer being logic heavy and the other a memory device.
The memory device could be optimized for low power output, which could allow reusing much of a standard chip design for the other layer.
That said, heterogenous can also be more complicated. The big juggling act is keeping each layer's hot spots over the cooler areas of the neighboring layer.
This can be difficult either because each layer is full of hot spots, or differences in layout and design require additional shuffling to align areas of low and high power.
There is also likely a dependency on the kind of designs being stacked. CPUs tend to have a broad area of lower power in their caches, while other types of chips like GPUs have hot regions that are more spread out.
On top of that, thermal expansion properties of each layer may come into play.
The odds of seeing an AMD-fabbed K10 being stacked on an R600 are small. Besides the heat output, the very different materials used would probably create too much mechanical stress.
Silicon is already intolerant of mechanical stress. For those that don't remember, there were some problems a few years back with TSMC's low-K dielectric, where the metal layers' different thermal expansion lead to unacceptable levels of chip failure.
If the problem is that noticeable on a die, it is likely to be worse between different dies.
I wonder if the level of logic versus SRAM might also influence mechanical behavior if the designs are very different.
Also, if IBM's announcement about insulation on air is put into production, it would likely make chips even more fragile.
The low-hanging fruit seems to be memory on logic, or a possible dual or quad-core homogenous stack, with the twist that it's not one processor stacked on top of the other, but stacked processors next to each other.
Anything with serious power draw is going to be thermally constrained, and more so than a planar chip. Hot spots in stacked logic are going to be hotter unless power draw is significantly reduced.
Intel's single-core Netburst example already showed that frequency had to be scaled back.
Another problem is that a highly stacked design has less area for pins. While stacking memory might be sufficient for many applications, it won't magically erase the problem that a chip with two stacked chips can only muster the external bandwidth for one.
More extensive layering would require better cooling and better mechanical measures. Either the cooler can be cooled below ambient (thermal stress), or something better can be thought up to somehow create a thermal interface that can tunnel between layers.
