3D Capabilities of nForce 4?
- Thread starter drhicking
- Start date
Well, you have to figure that the surrounding transistors of the pipelines and vertex shaders will be cut down too. Do you really need the same scheduler for a 16 pipe chip and a 2 pipe chip? No, a lot of that logic can be excised. Memory controller? Because it relies on the AMD AThlon 64 processor, it can be made a lot simpler. Will it feature a lot of the compression hardware for AA and AF? Not real sure, but why put all that on an integrated chip?
I am not part of the planning process at NVIDIA (which is probably a good thing), but I really don't see many technical reasons why the NV4x architecture couldn't be ported to a small, integrated part. It will be more expensive in terms of die and transistor space than a NV17m of course, but that is progress. If you think about it, the Voodoo 1 had two chips of 1 million transistors each. If you consider the current lowend 5200 has a whopping 45 million transistors, you can see how far that progress has gone! Adding another 10% to 15% transistors on a part that is 1 and 1/2 nodes down from the 5200 tech is not outrageous.
It is fun to discuss though.
I am not part of the planning process at NVIDIA (which is probably a good thing), but I really don't see many technical reasons why the NV4x architecture couldn't be ported to a small, integrated part. It will be more expensive in terms of die and transistor space than a NV17m of course, but that is progress. If you think about it, the Voodoo 1 had two chips of 1 million transistors each. If you consider the current lowend 5200 has a whopping 45 million transistors, you can see how far that progress has gone! Adding another 10% to 15% transistors on a part that is 1 and 1/2 nodes down from the 5200 tech is not outrageous.
It is fun to discuss though.
Actually Josh, for the most part I would say that you do in this instance. The scheduler's job is to know how to be schedule and issue intructions for the configuration of the execution units - the actual number of configuration units (or pixel quads) is effectively just a parameter to it. In terms of issuing it just needs to know the number of execution units and whether one is free, the mainstay of the logic will still be "how" to issue the instructions and that s probably more or less a fixed cost.
Hmm, but going by that logic, are you saying the scheduler has not changed from the TnT (2 pipeline) to the GeForce 256 (4 pipeline) to the NV40 (16 pipeline)?
It seems to me that it would require more logic to do more work, since more computing work is required to schedule 8x as many instructions. Not to mention the complexity of the instructions. It seems that a 16 pipe scheduler has to figure the best way to keep all 16 pipes busy, while a 2 pipe is almost a "1 is full, lets go to 2".
It seems to me that it would require more logic to do more work, since more computing work is required to schedule 8x as many instructions. Not to mention the complexity of the instructions. It seems that a 16 pipe scheduler has to figure the best way to keep all 16 pipes busy, while a 2 pipe is almost a "1 is full, lets go to 2".
No, the logic between different generations will have changed because NV40's pipeline configuration is significantly more complicated than NV10's and scheduling the instruction in order to get the best out of them will require better scheduling. I'm suggesting, for the most part, that you don't get the economies of scale with the schedulers within the same generation - i.e. NV43's scheduler is probably very similar to NV40's as the execution unit organisation / structure within each of the pipelinesis probably very similar; the only thing that changes is the fact that now there are fewer of them for NV43 than there are for NV40. However, there is still only going to be one scheduler (well, probably one for PS and one for VS), all the scheduler needs to know is that there are 2 PS quads to execute on in NV43 and 4, 3 or 2 in NV40 (with current configurations) and this doesn't necessarily take any silicon - in fact I would say that its a parameter in the BIOS.
I would expect (and don't take my word for it) the NV43 scheduler to require less cache, however. However, the name "scheduler" implies that it hardly needs cache. Thus, disregard what I just said since it's just another way of justifying what Dave said 
Also, Chalnoth, the only way I can see to reduce the processing power of a scheduler is either: 1) Lowering the clock rate (and I doubt it's asynchronous) or 2) Totally redesign it. So unless they made their design wonderfully flexible, I doubt they're going to manage to reduce its transistor count much. And, for a few transistors, it's questionable if they'd even bother (so, as Dave said; it might a BIOS parameter)
Now, the NV43 is 146M and the NV40 221M iirc; that means NVIDIA reduced the transistor count by about... 35%. That means the sheer maximum for a 2PS 1VS chip would be 60M. Which, I admit is way too big. But it's a maximum; they can cut the AA optimizations, nerf the dynamic branching efficiency (which would be reduced with the lower number of pipelines anyway I suspect) - and so on. 40M would thus seem reasonable to me.
Now, would a 2x1 NV4x run better than a 2x2/4x1 NV34? Most likely would be a mixed bag. Better VS, better PS, but worse texturing speed. Although probably not that much worse, considering the NV4x clocks better than the NV34 imo... Not as good as they had hoped perhaps, but still better than the NV34.
Uttar
Also, Chalnoth, the only way I can see to reduce the processing power of a scheduler is either: 1) Lowering the clock rate (and I doubt it's asynchronous) or 2) Totally redesign it. So unless they made their design wonderfully flexible, I doubt they're going to manage to reduce its transistor count much. And, for a few transistors, it's questionable if they'd even bother (so, as Dave said; it might a BIOS parameter)
Now, the NV43 is 146M and the NV40 221M iirc; that means NVIDIA reduced the transistor count by about... 35%. That means the sheer maximum for a 2PS 1VS chip would be 60M. Which, I admit is way too big. But it's a maximum; they can cut the AA optimizations, nerf the dynamic branching efficiency (which would be reduced with the lower number of pipelines anyway I suspect) - and so on. 40M would thus seem reasonable to me.
Now, would a 2x1 NV4x run better than a 2x2/4x1 NV34? Most likely would be a mixed bag. Better VS, better PS, but worse texturing speed. Although probably not that much worse, considering the NV4x clocks better than the NV34 imo... Not as good as they had hoped perhaps, but still better than the NV34.
Uttar
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