28nm @ TSMC: Very expensive or just wafer-limited?

Discussion in 'Graphics and Semiconductor Industry' started by AnarchX, Mar 24, 2012.

  1. 3dilettante

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    There may be some wrinkles specific to Nvidia, but the overal trends drawn are true if you are fabless company that needs to compete on the bleeding edge of manufacturing.

    GF, a foundry, has shown unsustainable cost growth in its own presentations.

    The move for tighter integration between design and manufacturing steps is something all the foundries are struggling with, and they aren't all doing this for Nvidia.
     
  2. Tahir2

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    Do you think then IHV's asking to be treated as IDM's by TSMC is correct? I can't see that working. Have AMD released themselves from that sort of arrangement with Global Foundries?

    Interesting to see the contrast in reaction - AMD talks about changing its strategic goals and not competing at the very high end against Intel (albeit they were mainly talking about CPUs rather than discreet GPUs at that time) and NVIDIA seemingly goes for TSMC's jugular with these somewhat childish slides - asking to be treated as an IDM and rough fair justice (what does that even mean?!)
     
  3. 3dilettante

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    AMD's CPU side probably gets the laugh track for hopping from the the model just prior to when the entire fabless industry realizes it has to be more like an IDM.

    edit: To note, years ago when the idea of a spin-off was rumored, I said that if AMD did this it might as well give up competing in x86, and it increasingly looks like it has.

    AMD didn't stop being an IDM because being and IDM wasn't the best way forward for manufacturing on leading-edge nodes, they did it because they were on the verge of imploding.
    What Nvidia says is necessary is not unique to them, and fabs like GF have been talking about or offering some of these steps already.

    This is also something I don't quite get about Nvidia's presentation, since it's not something newly discovered or a secret. What are they trying to do with these slides?
     
  4. Tahir2

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    Stating the obvious here:
    To change the status quo - at a guess and complete stab in the dark they are unhappy with the deal they have with TSMC and when negotiations didn't go their way they are looking for hearts and minds (the interweb) to rally against the tyranny of the evil semi fab.
     
  5. silent_guy

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    Not very likely.
    A whopping 2 1/2 months faster, no less. That explains everything.
     
  6. Tahir2

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    In the world of 12 month life cycles (or 18 if u like) it is impressive. Glad you agree! ;)
     
  7. 3dilettante

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    I don't think tech nerds have much pull with TSMC.
     
  8. Ninjaprime

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    Personally, I think its more of a "why 294mm^2 costs the same as 550mm^2 did, and we're just as mad as you guys" which is sort of damage control after the viral marketing BS they put out about AMD overcharging for 7970.
     
  9. silent_guy

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    I don't doubt that Nvidia would love to be as fast or faster than AMD, but if you know the amount of things that can (and do) slip in typical projects, the fact that there is only 2 1/2 months difference is really quite remarkable (and totally unlike the rest of most semiconductor companies.)

    In addition, you'll certainly agree that it's a bit of a stretch for different companies have dramatically different results for an identical process. After all, like I said before, the D0 doesn't change. In addition, (successful) tech companies are highly reactive wrt things going wrong: if you see that somebody does better, you better fix it. That's what project post mortems are for. In the case of Kepler, it's obvious that Nvidia spent a lot of effort fixing earlier wrongs. The visible ones are things like perf/mm2 and perf/W, but it's foolish to thing that they only looked at visible aspects.
     
  10. Arun

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    [Apologies for the hilariously long post, I haven't written anything so long on Beyond3D since I started working so I got carried away a bit! Obviously these are strictly my own opinions and I'm not speaking for anyone else here)

    Frankly NVIDIA's slides don't make much sense to me, likely because they're intentionally making things look worse than they really are. First of all I somewhat suspect they're somehow including the cost of the the I/O elements that don't scale (i.e. their 'scaling factor' is less than the actual transistor scaling). But more importantly, if the cost of 40nm transistors only became cheaper than 55nm transistors in Q4 2010, then why does their other graph show that they manufactured ~4x more wafers on 40nm than 55nm for the full year of 2010? Some of that can be attributed to their DX11 architecture being 40nm-only, but then why did they manufacture nearly 1/3rd as many 40nm wafers as 55nm wafers in 2009 when the costs were so much higher?

    The answer is very likely power consumption (and performance to a lesser extent but these are somewhat interlinked if you can adjust your voltage). You pay more per transistor but each transistor is more power efficient. This also implies that NVIDIA's entire argument is rather dubious: as there is a fundamental trade-off between area and power at several different design points (architecture, synthesis, voltage, etc.) then it would make more sense to compare cost for identical power consumption (roughly speaking as this is highly non-linear). And when you do that, the new process node will become more cost efficient much faster than it does when only comparing transistor cost.

    It's certainly true that both cost per transistor *and* power consumption scaled down faster several process generations ago. That doesn't mean process scaling is anywhere near dead yet and I'm sure that NVIDIA realises that. I suspect that what they're really trying to do there is pressure TSMC to accept lower gross margins on new processes to essentially subsidise early adopters (i.e. NVIDIA but also AMD/Qualcomm). They already do that but obviously NVIDIA would like them to do so even more.

    By the way, we do have some actual cost targets from TSMC for 28nm vs 40nm and for 20nm vs 28nm. They are quite revealing:
    It's important to realise that this is strictly capital expenditures and that early capacity is more expensive to build than mature capacity. The actual wafer cost also depends on the materials so for example the cost of High-K is mostly not part of that 'parity' estimate for 28nm. On 20nm where the main cost increase is on the litography side, it makes sense for a larger percentage of the total increase to be visible on the capital side. Also remember that various other expenses have also been increasing very significantly including process R&D (TSMC has been hiring very aggressively in the last few years for example, and non-salary expenses are also increasing a lot for everyone).

    Anyway it's pretty clear that a significant part of the wafer price increase on 28nm and the expected increase on 20nm is just TSMC trying to make more money before the process is amortised, and NVIDIA is fighting back to try to get TSMC to subsidise early adopters more. They'll probably just meet in the middle like they always do and this whole thing will amount to nothing (especially as it dates back from November and 28nm yields have increased significantly since then).

    I don't think there's any chance of NVIDIA leaving TSMC as long as Jen-Hsun and Morris Chang are both CEOs anyway since they're good personal friends. Morris won't be CEO forever though, he already came back from retirement when 40nm was becoming a huge problem in order to convince customers, e.g. Jen-Hsun, to stick with them rather than switch to GlobalFoundries.

    On the other hand, it's also very clear that 20nm cost will increase significantly more than 28nm cost, and wafer prices will increase more accordingly. This is despite 28nm introducing High-K and 20nm not using FinFET. I think TSMC would really really like to use either e-beam or EUV at 14nm rather than keep using more and more expensive variants of immersion litography (BTW, isn't it ironic how EUV was seen by some as likely being forever too expensive 5 years ago, and now the alternatives have become so expensive that lots of people have started looking at it as a way to reduce costs? TSMC still prefers e-beam which is interesting though, I actually hope that gets to market because it would have some more interesting consequences)
     
  11. Acert93

    Acert93 Artist formerly known as Acert93
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    TSMC's 20nm won't have FINFET?
     
  12. AlNets

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  13. Acert93

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    You enjoy crushing my dreams?
     
  14. Bob

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    Disclaimer: I don't know anything about those slides

    That scaling fact has been true for a long time, even ignoring IO. Wires don't scale in the same way as transistors, and different kinds of transistors also don't scale the same. Standard cells don't all scale the same way, so depending on the mix of standard cells in two different designs, they would scale differently going from one process to another.

    The newer processes also have more stringent P&R requirements. For example, some of the newer ones require that certain metal layers only have wires going in a single direction (horizontally or vertically, but not both). This reduces the overall density of transistors you can put on a die versus what it would be if that particular rule was not required, even if the individual transistors themselves would scale with that ideal factor (which they don't).
     
  15. Arun

    Arun Unknown.
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    That's a good point, and while tools have been improving to exploit that fact, they can't get around the fundamental limitations of the process.

    BTW, every new process node resulting in lower area utilisation does lead to an interesting problem where most semiconductor IP vendors quote their designs as pre-layout with 100% utilisation... ;)

    1D design rules are an interesting debate. GlobalFoundries initially claimed that Gate-First High-K was cheaper than Gate-Last and when they finally got problems on the implementation side, they suddenly started claiming it was actually higher density than Gate-Last despite the fact TSMC's lower density has nothing to do with Gate-Last and everything to do with very strict P&R requirements because they are using less aggressive litography for cost reasons (and also to make sure their customers don't do crazy cell designs that would result in horrible variability).

    I certainly agree that logic scaling isn't anywhere near 50% and hasn't been for some time (although 28nm is likely worse than 40nm in that respect) but looking at Kepler's transistor density versus Fermi, I doubt it's that bad (even assuming it would have increased on the same process). Part of the reason for that is obviously that unlike in the DX7-DX8 and early DX9 era, there's quite a lot of SRAM on modern GPUs, and that has continued to scale very well (with some trade-offs in terms of performance or power).

    You might be right that they're not including any I/O in there - while we do know what their wafer price ratio is from the other graph, it's impossible to tell what their yield estimates were, so there's a missing variable and we can only guess. Anyway it's all a bit academic at this point because 28nm still looks like a very good process from that graph (6Q between 55->40 and 40->55 crossover) and their real problem is with 20nm which makes sense given TSMC's 1.45x capital expenditure estimate.

    On a barely related note, I'm very curious about how significant TSMC's COWOS (Chip-on-Wafer-on-Silicon) initiative will be for the GPU market and what kind of adoption we'll see...
     
  16. Alexko

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    Yes, Kepler vs. Fermi isn't a very good comparison because of hot-clocks. Tahiti vs. Cayman isn't ideal either, because of Tahiti's bigger memory bus. But I think Pitcairn vs. Barts makes sense.

    Barts: 1700 Mtrans, 255mm², 6.67 Mtrans/mm²
    Pitcairn: 2800 Mtrans, 212mm², 13.21 Mtrans/mm², or about 1.98 × 6.67 Mtrans/mm².

    That's pretty damn close to perfect scaling.
     
  17. UniversalTruth

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    TSMC 28nm capacity in large shortage

    ???
     
  18. itsmydamnation

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    im assuming they just dont have Fab space lying around, so to transition more 28nm capacity they would have to reduce something else. I guess 28nm doesn't have the demand and/or the yields to reduce production of other nodes.
     
  19. pcchen

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    TSMC can't meet the demand on 28nm, so I think if this report is accurate, the most likely explanation is that TSMC expects its yield to improve so there's no need to expand too quickly now.
     
  20. silent_guy

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