RussSchultz said:
eDRAM and DRAM are different processes.
eDRAM is fabricated in standard CMOS logic. DRAM is fabricated in a different process that allows denser capacitors, which is how you can get oodles of bits in a die. Plus DRAM is generally fabricated on a very very aggressive fab that is designed specifically for DRAM.
But, even then, I am fairly certain that there is at least 1 transistor per cell.
Of course, I'm just going on what material I can find on the net, plus what basic knowledge I learned in school and on the job. Maybe ASICnewbie will speak up and share with us some more concrete info.
I've been told the same thing. Historically any type of ASIC embedded memory (e-DRAM, masked ROM, flash ROM, etc.) has required additional mask steps, which means longer production time and higher manufacturing cost.
1T-SRAM retains the almost the same bit-density (it's slightly less dense) as traditional e-DRAM, but does NOT require those additional processing steps. So it's more "ASIC CMOS friendly"
I think all embedded memories have higher transistor densities than 'regular' logic (analog or digital.) Consequently, embedded memories are more sensitive to manufacturing defects. The larger the die-area of the embedded memory, the higher the added risk.
If a customer design requires a large embedded RAM, TSMC recommends some type of "defect management", to avoid that proverbial "one bad apple in the whole bunch" from basically killing the whole die.
One approach (which is already standard practice for standard memory ICs) is to add 'spare memory' rows/columns to the die. During the testing process, test-equipment probes the die specifically for memory array defects. If there are enough spares to 'repair' the RAM, a laser maps the spare rows into the address-decoder array by burning tiny circuit fuses. This service is available at an extra cost.
Another potential approach (but not always feasible) is to add built-in intelligence to manage the defects. In this case, RAM-defects aren't repaired in hardware, but instead 'mapped out' during the ASIC's power-up runtime. This might work if your chip has an on-board CPU or intelligent controller. During power-up, the CPU first runs a diagnostic on the embedded RAM-array (like your motherboard BIOS's POST), in order to identify defects. Presumably, the CPU could would remember and avoid the memory-defects. As you can see, this arrangement is only practical for certain, specialized applications. But it eliminates the need for the laser-fuse circuitry and the associated laser-repair service.
If the embedded RAM is relatively small, it might be less expensive to simply 'do nothing'.
