AFAIK G100 has yet to tape out so it would be kind of hard to launch it in only a month and a half...
The G92 Architecture Rumours & Speculation Thread
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AFAIK G100 has yet to tape out so it would be kind of hard to launch it in only a month and a half...
Well, seems you have the upperhand, as I haven't worked on chips at all
. Anyhow, I guess both of us will have to wait and see what choice the IHVs make, as they're in a tad bit better situation to evaluate the benefits and weaknesses of either approach, eh?Even after years of seeing proof of accelerating technology miracles, it's surprisingly hard to envision what will be technologically possible even just a few years ahead. 30" LCD screens with 4M working pixels? Ultra-high DPI color screens in a cell phone with high quality video play back? Hell, just a year ago, I wouldn't have thought it possible to profitably produce larger-than-400mm2 dies for a consumer product!Well, seems you have the upper hand, as I haven't worked on chips at all
It's really the same with development: looking back just 5 years ago, it's a miracle we got chips working with the primitive validation techniques we were using back then. Yet verification methodologies are advancing so quickly that most design companies have a hard time staying up-to-date with the latest and greatest. These days, the holy grail is in formal methods, where you try to prove mathematically that you logic is correct under all states and conditions. It's pretty hard to get right and requires a very specific kind of expertise that's not commonly available, but it's incredibly powerful when it works.
I can't back this up with numbers, but my feeling is that despite the increasing amount of transistors per chip, the amount of bugs per transistor per chip and even numbers of bugs per chips has been going down. (The correctness of the software needed to control them is a whole other issue!)
All this to say: don't bet against 1 billion and larger chips. 2 or 3 years from now, the discussion will probably look so very quaint.
I'd bet on billion-transistor GPUs, within 2 process nodes.
It's already been done for Itanium, but the markup for chips of that size is very high.
Whenever the die size for a billion transistor GPU falls at or below G80, I'd figure it would be a good bet.
The primary obstacles are manufacturing ones.
The unknown is how bad process variation is going to get in that time frame. Defect rates are likely to be worked down to the point that they will match current defect densities.
Completely validated circuit and logic design means nothing if a pair of chips coming off the line can have maximum clocks varying by a factor of two or more and can have leakage variance of an order of magnitude.
The worse those get, the more likely the die size will need to be smaller and the more likely that chip counts rise.
It's already been done for Itanium, but the markup for chips of that size is very high.
Whenever the die size for a billion transistor GPU falls at or below G80, I'd figure it would be a good bet.
The primary obstacles are manufacturing ones.
The unknown is how bad process variation is going to get in that time frame. Defect rates are likely to be worked down to the point that they will match current defect densities.
Completely validated circuit and logic design means nothing if a pair of chips coming off the line can have maximum clocks varying by a factor of two or more and can have leakage variance of an order of magnitude.
The worse those get, the more likely the die size will need to be smaller and the more likely that chip counts rise.
The reason why no one knows exactly the G92 board of details is that Foxcoon
is responsible for the NV board production , no more revelant production by Felctronics. Except the 8800 Ultra , rest of the 8800 Series are not in production.
That would be against the trend of the last years: die sizes have been going up despite the increase of transistors per mm2.
Is there a problem with current process variations? If not, why do you expect this to happen now?
No, they have to be even better. (And they are...)
I haven't noticed major breakdowns in the correlation of timing models vs. reality, but you seem to have access to different data points. Please share.
That's just a matter of choosing the right process. These things are very predictable.
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Just on a quick tangent... My company is currently designing a chip that is 6.5cm x 6.5cm square (a giant multiplexer for hybrid imaging applications). We can fit 4 of them on an 8" wafer, and expect our yield to be <5% with cost at >$100k each. So...it can be done, for a price.
ERK
So has the talk of going multi-die.
Wafer diameters haven't grown beyond 300mm, so there are manufacturing parameters that have not scaled at all in recent years.
AMD's had known issues with its 65nm A64s.
http://investorshub.advfn.com/boards/read_msg.asp?message_id=21353453
I know it's a post in the intel section, but the numbers are indicative of process issues at 65nm.
The clock differential between the lowest rung of the released 65nm parts to the highest is only 600 MHz, though it is likely the lower qualifying parts would have been culled.
The power consumption, if voltages and clocks were equalized, would be much , much higher.
AMD's Barcelona is said to have circuit tuning that helps mitigate some of this variation, but it obviously is not out yet in quantity, and it has clocking issues.
Repeated steppings and process tuning are likely to push Barcelona up to and over 3 GHz.
The amount of work this will likely require is part of the increasing troubles with combating variation.
There is no expectation for this to be any easier at 45nm and below.
Most of the published yield curves by various CPU manufacturers show the defect rates on well-tuned processes tend to level off pretty close to one another.
The overall rate of physical defects in the wafers is something that seems to put a floor on the defect rates.
I don't have the numbers directly, but there were a number of interesting discussions on aceshardware on this.
Fabs don't normally release the distribution data, but there was a rough idea that the worst-case variation was something close to linear for clock timing, and much worse when it came to leakage between devices on the order of 10x (all else being equal).
Sadly, that forum has been shuttered.
This was debated by those who would have very good data, but I admit I may very well have misremembered the final amounts.
Device variation was characterized as having a linear factor between devices, something like a factor of two between the extremes, while leakage varied much more.
Most predictions by IEE and ISSCC papers (and Gordon Moore) are that variation is going to suck past 65nm.
There are loads of papers on techniques to make designs more tolerant of variation, which I hope are implemented for GPUs sooner rather than later.
Intel's success at getting quad core CPUs out over a year before AMD's single-die solution shows that there are benefits to multichip at 65nm.
Intel does not intend to go single-chip until the next process node, when the die size falls in line with current dual cores.
With the expectation that design, wafer, and fab costs for future nodes are going to rise, I'm betting conservatively that this constraint would be the same or similar for GPUs.
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Just do a little math and realize that a billion transistors can easily be done on 65nm with a decent die size reduction over G80 if you are NVIDIA. After all, the move to 65nm from 90nm should allow you to double the transitors or reduce ther die size by about 50%. Or a combination in between.
Perhaps a more interesting question is will there be a 2 billion transistor part at the 55nm half step?
I recalled the transistor count for G80 incorrectly, so my guess was overly conservative.
The die size would be in line with G80 as it is now, if Nvidia goes for the density route.
Unless the density scaling is unusually bad, the die would be over 400mm2, but less than 480mm2.
Nothing is "easily done" in MPU design & manufacturing.
If NVIDIA were to build a chip comparable in size to G80 on 55nm it would likely be on the order of 2 billion transistors, no?
And in terms of not been easy to design the parts, that is exactly why they will keep doing so. So they can keep ahead of the competition. Intel may be a node ahead in process, but that doesn't mean it will be easy (technologically or economically) to compete at the high end with NVIDIA.
No.
I don't expect Intel to compete with GPUs in the gaming market until at least their 2nd generation of products. The first gen is more of a "foot-in-the-door" product, intended to garner mindshare for the next release by creating brand awareness.
Oops, last one.
caboosemoose
Regular
I imagine the last one that highlights alleged mistakes in assessing the power consumption / leakage of AMD's 65nm process and claims that the reason why Barcelona isn't clocking up yet is due to SpeedPath probs, not process issues.
That message had its own set of replies that I found convincing enough.
http://investorshub.advfn.com/boards/replies.asp?msg=21524484
and then a later reply to a reply
http://investorshub.advfn.com/boards/replies.asp?msg=21530969
The comparison between the bins within the 65nm process at that time showed a very wide disparity.
The lowest bin had double the power draw at max, even with a lower voltage, a value with a known quadratic relationship to power draw.
At the same 1.1V, the lowest bin drew almost three times the power.
It is no stretch to say that this disparity in binning is due to process variation, and that it was problematic, even after months of tuning.
The recent 3.0 GHz K10 demo would actually strengthen the arguments made months ago.
Apparently, a stepping that either tanks at 2 GHz can also be made to reach 3.0 (with power restrictions eased, probably).
That is something I'd call variation.
http://investorshub.advfn.com/boards/replies.asp?msg=21524484
and then a later reply to a reply
http://investorshub.advfn.com/boards/replies.asp?msg=21530969
The comparison between the bins within the 65nm process at that time showed a very wide disparity.
The lowest bin had double the power draw at max, even with a lower voltage, a value with a known quadratic relationship to power draw.
At the same 1.1V, the lowest bin drew almost three times the power.
It is no stretch to say that this disparity in binning is due to process variation, and that it was problematic, even after months of tuning.
The recent 3.0 GHz K10 demo would actually strengthen the arguments made months ago.
Apparently, a stepping that either tanks at 2 GHz can also be made to reach 3.0 (with power restrictions eased, probably).
That is something I'd call variation.
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