eh oculus specs , r390x having 4 gigs of ram.... it took the wind out of my sales , I was happy and now i'm bummed .Are you some sort of wind-propelled retailer?
I'm just going to download the witcher 3 now and play on my 7950 for another year lol
AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread
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I'm just going to download the witcher 3 now and play on my 7950 for another year lol
The description of the test vehicle notes that it has 100k micro-pillars with no designed-in redundancy, which may make the 95% figure pessimistic if actual products add some redundancy.
All the descriptions of AMD's HBM offering do not have Globalfoundries as the interposer supplier, which may make the figures weaker approximations for what to expect with the upcoming product.
There is always the possibility of some unheralded OEM or niche-market salvage SKU with a weird salvage configuration if it comes to making some money from discards.
The test interposer's reticle-size dimension is a touch more modest that some of the research projects had projected for an interposer implementation at 26x32mm, but it's quibbling over a few tens of mm2.
AMD's artistic renditions of the HBM package seem somewhat disconnected with other images they provide, and what a known good stacked die from Hynix has been described as.
AMD round down a touch for its memory dimensions, with a 5x7mm module listed by Hynix as 5.48x7.29mm +/-25um.
http://www.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-11-day1-epub/HC26.11-3-Technology-epub/HC26.11.310-HBM-Bandwidth-Kim-Hynix-Hot Chips HBM 2014 v7.pdf
http://images.anandtech.com/doci/9266/HBM_12_FormFactor.jpg
The picture AMD provides of a mounted HBM module might not be what was being drawn, maybe a test device? Hynix has the PHY laid out the length of the module, and this dimension is usually kept matched by the side of the main SOC and very close by, as seen by Kalahari, other proposed HBM designs, or the photograph in AMD's slide. Not so in AMD's diagram, which has them hanging half-past the corners.
That pictured module isn't near a corner, assuming the dark expanse in the background is a main die. That module may be near another stack, but not consistent with how AMD's slide or Kalahari are drawn.
The interposer may be significantly smaller than Kalahari. Those dimensions, absent knowledge of how much room must be kept free for routing or other purposes, leave room to the imagination, which might be AMD's intent.
He was referring to your spelling goof.
It's sails, not sales. Anyway, 4GB, today, for an enthusiast card, they might as well not fucking bother at all. It's not enough for some games right now, much less what's coming in the future.
D
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In case you didn't notice, post-PS4/XBone multiplatform games are already capable of using over 4GB of VRAM for >1080p resolutions.
These graphics cards will be marketed towards the 4K folks, so of course it's a very important issue.
Joe Macri's statements are rather worrisome. It sounded a bit like "we'll just solve this physical limitation with driver magic", which is rarely good news.
Historically, Driver Magic has a tendency to be delayed, sometimes indefinitely.
What's important is how Fiji performs at 4K not how much ram it has. And as you said, AMD is probably going to market Fiji as the gpu for 4K. So, anything other than Fiji 'spanking' Titan at 4K would be ... surprising. If it does, will you drop the ram 'issue'?
D
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Probably not. The most high-profile games will need more than 4GB of RAM and the end result is that in mid-term the Fiji will plummet in performance within a year or so.
Just like the GK104 <-> Tahiti, or GK110 <-> Hawaii comparisons then and now.
At 4k higher texture resolutions are necessary to keep the texture fidelity up, otherwise you will see more blurring or stretching, think of it like you are zooming into a model with a camera, the amount of pixels on the screen will be rendering less pixels on a texture.
was it a goof ? Or am I just that good ?He was referring to your spelling goof.
Anyway, 4GB, today, for an enthusiast card, they might as well not fucking bother at all. It's not enough for some games right now, much less what's coming in the future.
I can't spell my way out of a paper bag lol
No, you will not perceive same texture as more blurry just because pixels:texels ratio increased.
Sorry you are right didn't mean that, I mean is the extra res doesn't do anything unless you have higher res textures.
I'm just throwing ideas out here, but I can only think of games using MRT/deferred shading, and scale all their buffers (post-processing) accordingly while they're not clearing out those intermediate buffers or reusing the same RT space. Not a PC game, but Killzone Shadowfall came to mind as their pre-release demo build was mentioned as using up to 800MB in framebuffers, which seems a tad wasteful for their 4.5GB usable game memory. They must have reduced that for shipping.
Otherwise... yeah. I dunno. There's various shadowmaps (cascades etc), but that's a separate thing I suppose (devs don't go too crazy in exposing larger than 4K x 4K maps as a game setting).
:s
There may be a limited subset of users that kick settings as high as they can go on games that come with those very large post-launch content packs.
It's not clear that the returns match the investment, but I think the knobs exist that can be turned on that pain point. Then, possibly force on additional AA methods at 4K to make things heavier.
I imagine there's a line where such efforts would finally be laughed off by all but the most motivated fans of the competition, but where AMD's promised driver efforts, the ongoing pickiness about hitches and latency, the rate of increase in the genuine working set of intensive graphics loads over time, and where antagonistic marketing pressure balance out is uncertain to me.
It's not clear that the returns match the investment, but I think the knobs exist that can be turned on that pain point. Then, possibly force on additional AA methods at 4K to make things heavier.
I imagine there's a line where such efforts would finally be laughed off by all but the most motivated fans of the competition, but where AMD's promised driver efforts, the ongoing pickiness about hitches and latency, the rate of increase in the genuine working set of intensive graphics loads over time, and where antagonistic marketing pressure balance out is uncertain to me.
Assuming the HBM1 memory from Hynix and AMD's controllers don't have for some wonky reason quirks that keep them out of the HBM specification proper, the expanded capacity and higher bandwidth are already provided for. What might not show up would be extra features like the pseudo-channel mode from some of Hynix's slides, although there were rumors stating that was already in AMD's controllers.
Given the cooperation between AMD and Hynix, it seems possible.
That time frame is almost time for a rebrand, although that puts to the test where the cost structure and cost improvements for this tech go.
Jawed
Legend
Two things worth noting here in this picture:
http://www.hardocp.com/image.html?image=MTQzMTYyNzY0OE5JR2pTVWE4RGdfMV8xMl9sLmpwZw==
First, notice just how close to the edge of the interposer that HBM chip is, and how little space there is between it and the much larger chip (0.25mm?).
Second, notice that the HBM chip isn't at a corner. In the top left of the picture there appears to be another HBM chip, too...
http://www.hardocp.com/image.html?image=MTQzMTYyNzY0OE5JR2pTVWE4RGdfMV8xMl9sLmpwZw==
First, notice just how close to the edge of the interposer that HBM chip is, and how little space there is between it and the much larger chip (0.25mm?).
Second, notice that the HBM chip isn't at a corner. In the top left of the picture there appears to be another HBM chip, too...
I don't think HBM2 would help a lot with performance, but at least it will help them out with the memory size. Of course, 9 months from now, may be too late: they'll soon start running into the first 16/14mm chips. I think that's the biggest problem for Fiji: it's released too late in the 28nm cycle.
What AMD has diagrammed and what AMD has photographed are not readily reconciled as being the same thing without further clarification. The distances between the two stacks do not match a dimension that is probable for what has been rumored as Fiji, or what AMD has drawn as a representation of an HBM GPU.
The former seems to make the most sense. The interposer permits very short connections between memory and GPU, and what better way to take advantage of it by making the distance between memory and GPU as short as is practical?
The AMD diagram that has half the HBM interface with no GPU to run straight into stands in contrast to other data points.
Aside from power, which TSVs should drill down from the base die, the far side of the stack may not worry much about the edge of the interposer.
Well yes, the corner placed HBM never made much sense from a interconnect sense. It is also the most interposer space inefficient.
I would imagine they would use the smallest interposer possible for their largest ASIC, or I guess they could have reversed that and built the largest interposer possible, within reason, and made sure their new large ASIC fit in it.
I would imagine they would use the smallest interposer possible for their largest ASIC, or I guess they could have reversed that and built the largest interposer possible, within reason, and made sure their new large ASIC fit in it.