PiNkY said:Granted i don't know a lot about power5 bus architecture, but as they seemingly use a shared l2 cache, this is certainly thighter coupling then "copy & pasting" three "G5s" on a core and connect them to a shared bus.
The "G5" cores (PPC976 probably) interfaces to the L2 and write buffers, the L2 and write buffers interfaces to the bus controller interface. The CPUs are actually abstracted from the CPU interface by intermediary hardware so that there are three CPUs on the same die needn't mean that much really.