Xenon or CELL..

[j^aws]

G5= 2 VMX+2FPU
PPE=1VMX+1FPU

G5 has 2 VMX units!

This is a single G5 core, right? Now I have to read that! <shakes fist>

<shakes fist even harder>

That's BS!

Check the diagram on page 8, it clearly shows 1 VMX unit! So,

G5 = 1*VMX + 2*FPU

1 VMX unit but with dualpipeline

That's still 1 VMX unit and NOT 2 VMX units.

How do you know that VMX unit in the G5 is different to the VMX unit in the PPE? And the VMX unit is still ~ 8 Flops per cycle right?

i dont know , G5 too complicated, i mean G5's VMX up to 16 flops/cycle

From page 9 of the pdf,

...
Each Velocity Engine pipeline speeds up this task by processing up to 128 bits of data, in four 32-bit integers, eight 16-bit integers, sixteen 8-bit integers, or four 32-bit single-precision floating-point values, all in a single clock cycle.
...

That's still 4-way SIMD per cycle and with FMADD, that's still 8 Flops per cycle.

 

[version]

in 1 pipeline, but have two

 

[j^aws]

in 1 pipeline, but have two

Yes but NOT on the same cycle...alternate cycles, yes, but I don't see where the VMX is SMT?

 

[version]

"Beyond that, he or she claims, comes the sequence-following 990, to be fabbed at 65nm in 2005/2006 and running from 6GHz initially and rising to 10GHz. The PowerPC 9900 will take the platform to 45nm in 2007/2008. It will run at 9-10GHz and ramp up over time to 20-25GHz in 2010-2011."

"Improvements in the PPC 980 include Hyperthreading, eLiza error correction, and more massive parallelism. IBM's implementation of hyperthreading provides a 30% gain over Intel's. eLiza technology will reduce the bottlenecks when the branch prediction unit fails. Altivec will split into 3 pipelines (vs 2 in the 970), 4 Integer and 4 Floating point units. 980 will have to be built on a 90nm processor due to heat dissipation requirements."

 

[j^aws]

^^^Nintendo's Revolution might use a modified, PPC 980 core...but the G5's VMX unit is still 8 FLops per cycle!

 

[version]

"Only one permute and one VALU instruction may be dispatched per cycle. Up to two vector loads or one vector load and one vector store can also be dispatched that cycle" - from ibm's G5 manual

8 flops, permute is integer you are right

 

[pc999]

Anyone have performance numbers for the PPE alone?

1 PPE being 2 way SMT, dual-issue ~ VMX + FPU ~ 8+2 ~ 10 Flops per cycle

The VMX can do FMADD but I'm assuming the FPU can do an FMADD also, i.e. FMADD ~ 2 Flops per cycle.

Thanks