XBox 360 eDRAM

[Wunderchu]

from what I can tell from reading through all those articles linked to in this thread: http://www.beyond3d.com/forum/viewtopic.php?t=23138 ,

the bandwidth between the daughter die (the one with the 192 processing units) and the eDRAM is 256 GB/s ..... that's where the 256 GB/s number comes from..

 

[3dcgi]

Remember the 256GB/s bandwidth figure from earlier? It turns out that that's not how much bandwidth is between the parent and daughter die, but rather the bandwidth available to this array of 192 floating point units on the daughter die itself. Clever use of words, no?

http://anandtech.com/tradeshows/showdoc.aspx?i=2423&p=2

 

[Wunderchu]

Remember the 256GB/s bandwidth figure from earlier? It turns out that that's not how much bandwidth is between the parent and daughter die, but rather the bandwidth available to this array of 192 floating point units on the daughter die itself. Clever use of words, no?

http://anandtech.com/tradeshows/showdoc.aspx?i=2423&p=2

ya (Vysez posted that quotation on the previous page, too)

 

[jvd]

but what is the bandwidth between the edram and the gpu ?

 

[mech]

http://www.firingsquad.com/features/xbox_360_interview/page3.asp

ATI: The 2-terabit (256GB/sec) number comes from within the EDRAM, that’s the kind of bandwidth inside that RAM, inside the chip, the daughter die. But between the parent and daughter die there’s a 236Gbit connection on a bus that’s running in excess of 2GHz. It has more than one bit obviously between them.

236? Is that a typo?

So it's 32gig/s between the parent and daughter die (if that is a typo and they meant 256)

Interesting way they've done it, it's not quite embedded in the traditional sense, and it's not quite an external chip in the traditional sense...

 

[Megadrive1988]

Just found out that the eDRAM bandwidth between the shader core and eDRAM core is 256GB/s, real bandwidth (not extrapolated) - the interlink between the two is running at 2GHz.

whoa

 

[DegustatoR]

Well supposedly R520 is slower than R500...

Jawed

And just imagine if the R520 is faster than the NVidia G70. Imagine the windfall that ATI & MS would have then.

RSX is not G70. G70 is running at 430MHz, RSX is supposed to be running at 550MHz.

 

[PC-Engine]

Pretty amazing piece of engineering ATI has done with Xenos.

 

[aaronspink]

256gb/s / 2 Ghz = 128 bytes transferred each clock = 1024-bit bus interlink. Umm, no, this doesn't sound right Dave.

Or do you mean Gigabit per second? That would mean its a 128-bit bus @ 2ghz, and the real bandwidth is 32gb/s.

How in the hell do they have 1024-bit interconnect? I can't see it as being possible. It has to be effective bandwidth, meaning the real signalling is much less, but the amount of data being transferred is 256Gb/s.

If the design is an MCM, then it is entirely possible. Probably not strictly needed but possible. In the case of an intra-MCM connection, the limitation is primarily on the numer of die side bumps that are required.

IIRC, the original Pentium Pro had a 256b bus between the L2 Die and the procoessor Die, and that was done in wire bond technology. With modern C4 bump technology, 2 512b busses or so are reasonable. Though, I would probably do a 512b write bus and a 256b read bus.


Aaron Spink
speaking for myself inc.

 

[blakjedi]

ok after going through this and the millon other threads like it....

what is the design of those 192 FPUs on the daughter die, and what are supposed to be doing?

Are they dedicated strictly to z/stencil/aa or are they programmable (any fpu task) also?

and do they run at the speed of the xenos or system or the RAM?

I dont think the PR guys at MS (bach, allard) really know what this chipset is capable of so they tout what they know... servicees like xbox live

 

[Dave Baumann]

I dont think the PR guys at MS (bach, allard) really know what this chipset is capable of so they tout what they know... servicees like xbox live

They don't, and its pissing ATI off...

 

[Xmas]

ok after going through this and the millon other threads like it....

what is the design of those 192 FPUs on the daughter die, and what are supposed to be doing?

Are they dedicated strictly to z/stencil/aa or are they programmable (any fpu task) also?

Don't forget blending. It's usually in the form of A*B+C*D. 3 ops per channel, 4 channels per pixel, 8 pixels per clock. 96 ops for blending only, plus it might be necessary to invert some of those values.

 

[Love_In_Rio]

Sorry, wrong post

 

[Acert93]

They don't, and its pissing ATI off...

ewwwwwwwwwwww Dave, tell David O. that we all at B3D said to tell Allard to take a seat and let him do the talking from now on

As much potential the Xbox 360 has (which is a lot) I think the talking heads at MS totally trashed E3. Yes, Xbox Live with rock, but everything from their system to their games was ill presented. MS has some slick stuff, some great stuff, and all I feel is underwhealmed. Maybe the mass market is more excited, and game sites are talking about the apples-to-apples GOW-to-UT2007, but I think MS dropped the ball on the hardware presentaiton and the games presentation.

After following the HW closely I think on the balance of give or take they can make just as good of an arguement for Xbox 360 as Sony can for the PS3. I see a sad trend in where it appears only Sony is leading their consumers with a strong sense of confidence. The talking heads in MS gaming department seem to be totally confused and unorganized.

Like they were buying their own MTV crap.

 

[cthellis42]

They don't, and its pissing ATI off...

ewwwwwwwwwwww Dave, tell David O. that we all at B3D said to tell Allard to take a seat and let him do the talking from now on

Hear, hear! Orton'd be much smarter about the tech, and look a lot less like a pirate.

But this is Microsoft's baby, and Microsoft tends to forget what to push other than software. Hehe...

I'm sure Nintendo would be fine letting them talk up Hollywood as much as they feel like.

 

[Geeforcer]

So, has 256GB/s *real* shadercore->RAM core bandwidth been confirmed?

 

[cthellis42]

Seemingly not yet.

 

[JF_Aidan_Pryde]

256gb/s / 2 Ghz = 128 bytes transferred each clock = 1024-bit bus interlink. Umm, no, this doesn't sound right Dave.

Or do you mean Gigabit per second? That would mean its a 128-bit bus @ 2ghz, and the real bandwidth is 32gb/s.

How in the hell do they have 1024-bit interconnect? I can't see it as being possible. It has to be effective bandwidth, meaning the real signalling is much less, but the amount of data being transferred is 256Gb/s.

If the design is an MCM, then it is entirely possible. Probably not strictly needed but possible. In the case of an intra-MCM connection, the limitation is primarily on the numer of die side bumps that are required.

IIRC, the original Pentium Pro had a 256b bus between the L2 Die and the procoessor Die, and that was done in wire bond technology. With modern C4 bump technology, 2 512b busses or so are reasonable. Though, I would probably do a 512b write bus and a 256b read bus.


Aaron Spink
speaking for myself inc.

Thanks for that.

Can you go into more detail how MCM tech works? Obviously on the PCB, placing 1024 wires between two chips is crazy. But what element of MCM tech solves this?

Here's a pic of the Pentium Pro with 1MB cache

[/img]

 

[Teasy]

Some people seem to have missed the comment mech quoted above. That comes direct from ATI and it says pretty clearly that the link between the GPU and 10MB memory isn't 256GB/s.

 

[JF_Aidan_Pryde]

http://www.firingsquad.com/features/xbox_360_interview/page3.asp

ATI: The 2-terabit (256GB/sec) number comes from within the EDRAM, that’s the kind of bandwidth inside that RAM, inside the chip, the daughter die. But between the parent and daughter die there’s a 236Gbit connection on a bus that’s running in excess of 2GHz. It has more than one bit obviously between them.

236? Is that a typo?

So it's 32gig/s between the parent and daughter die (if that is a typo and they meant 256)

Interesting way they've done it, it's not quite embedded in the traditional sense, and it's not quite an external chip in the traditional sense...

If it is 256-bit bus between GPU and eDRAM module at 2GHz, would it be 256/8 * 2 = 64GB/s?