"Xbox 2 Patent?"

Re: Another Xenon Patent?

Wunderchu said:
http://news.teamxbox.com/xbox/7421/Xbox-2-Patent

Umm, that's the same patent that was posted here on 12/30. TeamXbox is just a little late with the news. Though I do give them props for actually trying to understand it and providing some analysis. A lot of other sites have just latched on the idea that it had a Xbox1 photo in it and it mentioned an internal hard drive. Thus believing Xbox2 would have one as well. :rolleyes:

Tommy McClain
 
It's already been analyzed here, and by far more capable persons.

I think the thread was titled "A few new things" or something like that.
 
it might be old now, but i hadn't seen the diagram

xbox2patent_01.gif



so it is possible for an additional CPU module with another 3 cores. hmmm. maybe Microsoft is keeping that as an option should PS3 prove to have a truly 'stunning' spec, instead of just 'very powerful' as expected ?

edit: wasn't it Brimstone that predicted two CPUs, each triple core?
oh yes it was:
http://www.beyond3d.com/forum/viewtopic.php?t=19411&postdays=0&postorder=asc&start=0


yeah i'd love a Xenon with two CPU modules. plus a single G/VPU that has twice the number of pipelines and shader units that R520 will have. if R520 has 32 (8v + 24p) then give Xenon 64 unified units. or at least 48. get plus 512 MB memory. yeah, in my dreams right.
 
Actually the third CPU core says "CPU n" not stating how many "CPU cores" each of the "CPU Modules" have. It looks like they've left their options wide open for using multiple "CPU modules" initially to then shrink to fewer "CPU modules" by moving more CPU cores per die at a later date. No clue if they are going to do that, but it looks like thats what they are leaving themselves open for.
 
well Dave, to me it looks like each CPU module has 3 cores. 1 of them for general purpose processing and the other two for geometry/vertex processing.

what am i not seeing?
 
Megadrive1988: note the '...' between the second and third CPU cores, and the fact that the third one is labelled 'CPU n' rather than 'CPU 3'. The text of the patent also talks about the fact that the architecture could be scaled to as many CPU cores as were required.
 
oh okay. i see now. thanks guys! :oops:

<---- the idiot 8)


edit: it looks like the old GIbiz report about 4 or more CPUs could easily be correct. GDC / March can't come soon enough.
 
Btw, the patent gives an example the CPU 1(108) can be the host CPU and CPU 2(110) and CPU n(112) can act as geometry processors. However that doesn't necessary mean they would have to be used in that configuration.

patent said:
[0039] As noted above, while n CPUs (108, 110, . . . 112) are illustrated in FIG. 1, any number of CPUs can be included (including, for instance, only two CPUs). Further, additional CPUs can be devoted to performing host-related functions (that is, more than one CPU can be allocated to performing host-related functions). In one implementation, all of the CPUs (108, 110, . . . 112) are structured in the same manner. That is, all of the CPUs operate using an identical instruction set, but perform different functions based on the programs provided by the game developer. For example, a designer may prefer to design the CPU module 102 such that all of its CPUs have the same structure to facilitate testing of the CPU module 102, and later programming of the CPU module 102 by a game developer. However, in another implementation, the host CPU(s) can be designed to have a different architecture and functionality than the geometry-generating CPUs.

[0040] In one application, the system 100 can be configured to statically assign roles to the CPUs (108, 110, . . . 112), e.g., by assigning a CPU to the role of either a host CPU or a geometry-generating CPU. In another application, the system 100 can allocate these roles in a dynamic fashion, possibly on a frame by frame basis, or even many times within a frame (e.g., on an intra-frame basis). Thus, in one application, all of the CPUs (108, 110, . . . 112) can be assigned the role of handling host-related tasks. This might be appropriate in those cases where a programmer does not wish to make use of the special features provided by the geometry-generating CPUs 2 and n (110, . . . 112). In another case, the system 100 can assign the role of geometry-related processing to all of the CPUs (108, 110, . . . 112) for some portion of the frame time. In another case, as will be discussed below, the system can include two or more CPU modules 102. In this case, the system 100 can allocate the same role to all of the CPUs in one of the CPU modules 102 (such as geometry processing). In this scenario, it may be considered beneficial to locate the CPU module 102 assigned the role of host processing closest to a system memory 130 (because, in some environments, the host may be more negatively impacted by random access read misses than the geometry processing functionality, and therefore has more of a need for lower latency compared to the geometry processing functionality).

Tommy McClain
 
nice. it would seem to me that Xe's CPU architecture is very modular and scalable, like ahem, another much talked about CPU architecture ;)

it would also seem to me that Microsoft has wisely left its options open. perhaps open enough that they could 'react' to PS3 spec unveiling by configuring Xe's CPU system to compete with PS3's CPU system, if they so choose to.
 
This is making me think they are goig for an agmalgamation of Sony's idea for cell and AMD and Intel's ideas of a multi-core processor.

(did I spell that right we really need a spell checker)
 
Megadrive1988 said:
nice. it would seem to me that Xe's CPU architecture is very modular and scalable, like ahem, another much talked about CPU architecture ;)
Yeah, seeing the filed date June 30, 2003, they seemed to have studied a lot about the other CPU architecture by then ;)

However, in another implementation, the host CPU(s) can be designed to have a different architecture and functionality than the geometry-generating CPUs.
This line of the patent I missed in the other thread is an Emotion Engine/Cell PE like setup (a general-purpose core and multiple special-purpose cores), while the first implementation mentioned in the patent describes a scenario where software dynamically assigns different tasks to identical cores. I think this implementation by identical processing units (= simple multithread programming model found in Windows) is more likely if Microsoft hates a PS2-like architecture and developer nightmare.

Also, you should look at this paragraph in the patent
[0056] Further, the ensuing discussion (e.g., with reference to FIG. 5) presents examples that use multiple CPUs, each of which may include multiple threads. However, in another implementation, the CPU module can employ only one CPU having multiple threads. In this single CPU scenario, one or more of the threads can be provided to perform the role of host, and one or more threads can be provided to perform the role of generating geometry data. The generic term "processing element" has broad connation as used herein; for instance, it can refer to a thread implemented on a single-threaded CPU or on a multi-threaded CPU, or some other kind of processing functionality.
I assume this scenario is only an extreme example by which the author tries to explain the term 'processing element' and unlikely for the Xenon CPU. But still, there's the possibility that the Xenon CPU has only 1 or 2 cores, rather than 3 or 4, by looking at only this patent.
 
It's quite disappointing to notice a lot of patents I posted here go completely unnoticed. And then they bounce back here from another (loosy) forum :(
 
Back
Top