I just looked through the IBM press release again, and I'm now almost certain that we're looking at an SoC and the eDRAM won't be L3 cache:
The way they describe the purpose of the eDRAM doesn't scream L3 cache to me. Were it cache, they'd probably have written just that. "Feeding data" sounds like a memory pool to me. And the press release calls it a "silicon package", which could very well mean an APU, in which case that memory pool would almost certainly be shared between CPU and GPU.
The devil lies in the details. BW to edram in 360 wasn't much more than the bw to dram.
It all boils down to how much off die bw nintendo is able to provide. If it's not much more, then there's not much point in using edram in the first place.