I find it a bit disheartening that the CPU might be a bottleneck.
I wonder what kind of CPU Nintendo selected.
BgAssassin did your hear anything more specific wrt to the CPU?
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Having gone with IBM and wanting lower operation ( my assumption) they should have shamelessly reuse the SPUs.
I haven't read a presentations on the matter for a long while but how SPU time does it take to the Cell to keep up Xenon if you put aside lot of the graphic loads that would be handle by the GPU in a WiUU?
Clock for clock I would say that 2 is more than enough.
I don't know if it would be doable to have the SPU running at 3.2GHz with the CPU running significantly slower. Either way they may have gone with 4 SPUs within a CPU running slower.
Basically a new Cell. I believe it would have keep up not only with Xenon but also with PC parts for a while.
The Cell is like
this @45nm. It's a gross estimate but Imeasure a power7 core (with its L2) ~29sq.mm.
4 SPUs measure pretty much the same size (a bit below).
Within the Cell die size you substitute 4 SPus for of power7 core and fill what was the L2 + PPE with L3 you would fit quiet an amount of cache (gross paint estimate ~4MB).
Either way it's just to give idea a single CPU achieving nicer performances per cycle than a PPU and 3/4 SPUs might have been doable within +/-100 sq.mm of silicon.
I don't know Wiiu CPU size but I'm confident they could have trade two of their cores with at least 2 SPUs. SPUs are that tiny. Even embedded processors with 512KB of cache can't be as tiny (@45nm that's it).
Spus are 6.5 sq.mm with their local store
Still SPUs are very un-Nintendo but it was an obvious solution to meet the requirement of this gen CPU and a bit forward actually.