What is "Three cores (fully coherent)." ?
Cache Coherency probably. i.e. updating local core cache if values change in one of the caches of some core. Or something like that. It just makes sure the data is consistent.
What is "Three cores (fully coherent)." ?
I was watching 720p feed and what TT Games had managed to get Lego IQ was just unbelivable bad. Tearing, pop-in, framerateissues in a really simple game.
I thought Batman looked really bad, too, but I wasn't sure if the Wii U was just producing ugly games or if there was some aweful compression happening to the gameplay on Spike's stream (which otherwise has been beautiful in HD).
Also could be from an older dev kit.
More 8 render targets
I don't get this:
Write gatherer per core.
Locked (L1d) cache DMA per core.
What does that mean?
from the leaked specs, i read that the gpu has a tesselation unit (even if IIRC the r700 family didn't). Does that means, that there is hope to actually see tesselation in Wiiu games? Xbox 360's gpu also had a tesselation unit, but as far as i know no game actually utilized it (maybe because of the huge cost in terms of computational power required)
The rv700 had a tesselator, as did the r/rv600 family before it. Less capable though than the rv800 family tesselator.
IIRC the Xbox360's tesselator was used in a couple of games: Viva Pinata, Forza 3, Halo Wars and Halo Reach.
IIRC the Xbox360's tesselator was used in a couple of games: Viva Pinata, Forza 3, Halo Wars and Halo Reach.
The 32MB of eDRAM array in POWER7 is taking a mere ~66mm² on the die (without the L3 tags). And this is an implementation that has been accommodated for a much less tolerant high-performance architecture design. It's definitely doable/affordable for a tiny console, on any modern manufacturing process. Actually, I would even go for 48MB -- perfect size for a full 1080p back-buffer in FP16 format, with some leftover space for 2x multi-sampling.The 32MB of EDRAM seems to have take a way to significant part of the silicon budget. Possibly the part of the budget which would have allowed the WiiU to be a more proper in between design.
ThanksWrite gatherer per core is a technique to speed up writing out to memory by uh... gathering writes and sending them out as one. I'm probably hedging on details because the usage is basically just "you turn it on, and it makes writing memory faster" in some circumstances. It's similar to write-combined memory on xbox.
Locked cache DMA is a technique where the L1 cache is "locked" and used as a very fast area of temporary memory, similar to scratchpad on PS2 or a little like an SPU.
As for what it means... it means something that I'm not gonna say.
Why the secrecy? It means U-CPU can do everything Gekko could. BTW, POWER7 also has lockable & DMA-able caches.Write gatherer per core is a technique to speed up writing out to memory by uh... gathering writes and sending them out as one. I'm probably hedging on details because the usage is basically just "you turn it on, and it makes writing memory faster" in some circumstances. It's similar to write-combined memory on xbox.
Locked cache DMA is a technique where the L1 cache is "locked" and used as a very fast area of temporary memory, similar to scratchpad on PS2 or a little like an SPU.
As for what it means... it means something that I'm not gonna say.
Should we assume post process AA is the best way to go in order to get maximum performance out of the Wii U?