Wait wait wait, in the previously posted tear-down there are 4 separate DDR3-1600 chips (each one 512MB) on the board. Would it be that each of them have a bandwith of 12.8 GB/s individually and so there is a total bandwith of 50.4 GB/s for the RAM, or would it just flatly be 12.8 GB/s?
If it's the first case, then I can see why the ports still came out the way they did. They were not developed to access the RAM in such a fashion, so the de-facto bandwith was very low.
Would this have anything to do with the DDR3 memory controllers that IBM uses with Power7? Because we dont know yet what technology the CPU shares with Watson.
Nehalem-EX has 4 buffered DDR3 channels per chip, where, using on-board buffers, every channel splits into two actual 64-bit DDR3-1333 DRAM paths. If the buffers had the abilities like FBD AMB (Advanced Memory Buffer) chips, you might be able to do simultaneous read and write transactions on each channel, effectively doubling the bandwidth. Either way, you're looking at some 50GBps of memory bandwidth per CPU chip, not bad at all.
In the case of POWER7, though, there are two 4-channel DDR3 memory controllers, for a total of 8 channels of memory and a claimed 100GBps total memory bandwidth.
Power7
Dual DDR3 Memory Controllers per chip. Each DDR3 Memory Controller:
8 KB scheduling window
Connects to up to 4 proprietary memory buffer chips. Differential-signaling interface. Buffer chip:
6.4 GHz * 2 bytes buffer chip -> Power7 chip bandwidth
6.4 GHz * 1.5 bytes buffer chip <- Power7 chip bandwidth
dual high-frequency DDR3 DIMM ports (DDR3: 800, 1066, 1333, 1600)
Maybe WiiU is using one of them?