Just a request for some speculations. . .
Is there any precedent for this in CPU architecture?
The only reasoning I can think of is that there really are only two FP32 registers and an internal cache for temporarily storing data when more than two registers are needed. If this were true, the more registers needed, the more swapping back and forth between the registers and the cache would be necessary. Still, knowing the possible ramifications of this, making such a design decision is quite incomprehensible. . .
Is there any precedent for this in CPU architecture?
The only reasoning I can think of is that there really are only two FP32 registers and an internal cache for temporarily storing data when more than two registers are needed. If this were true, the more registers needed, the more swapping back and forth between the registers and the cache would be necessary. Still, knowing the possible ramifications of this, making such a design decision is quite incomprehensible. . .