Why does each CELL core pack 8 VUs????
- Thread starter DeadmeatGA
- Start date
Grall said:
Based on interviews which describe architectural development well after the patent was filed.
Your sarcasm about Deadmeat's opinion on what is possible or not is misplaced, he bases his opinion on deduction ... his assumptions might be oversimplified and plain flawed, but that is still better than what you put up against it (which is to say nothing).
I remember it mentioned somewhere in the patents yeah. That ex-NDD programmer also refferd it in his analysis of the patent...nAo said:
Anyway I'm taking the patent contents as a guidline rather then solid fact at the moment
, so I'll stick to "it would be nice" on this one and believe it when I see it.I do agree that external feed can be preferable sometimes - but seeing that DMAC itself is on PE maybe both might be possible?
Just to round up Marco's post - the total FMAC/FDIV count is 5/2 for VU1 (EFU has one FMAC and one FDIV) and 4/1 for VU0, so 9/3 total.
The remaining FMAC/FDIV pair is the FPU on R59k core.
MfA said:
What interviews? Where do these alledged engineers alledgedly say they have no plan to work after? That's just plain silly, I can't think of a single reason ANYONE would say such a thing when it comes to a huge project like this, and furthermore, I can't think of a single reason it would be true either. The people running this project didn't fall off the back of a wagon yesterday, they're not idiots.
Of course they have a plan! How could you POSSIBLY hope to design a several hundred-million transistor microprocessor costing billions to develop if you have no plan???? You're starting to sound as rediculous as deadmeat!
You think they're winging this, flying by the seat of their pants? Think again, bub.
"Deduction" isn't the right word starting with letter "d". Try delusion instead. I still fail to see your point btw, if indeed there even is one.
Looks kinda like you're trying to spread fud. Would be helpful if you explained exactly what it is you're trying to say, then I wouldn't have to guess.
Uh, right...
*G*
Grall, MfA's point was loud and clear.
It basically works like this. Much like your previous post which is chalk full of sarcasm and pomp; it lacks any reasoning which is in anyway valuable to the discussion.
If one was to examing deadmeat's reasoning. One would say we disagree with his conclusion, nevertheless it's strong and well supported by the premises his presents.
Even the reasons he provides for his arguements don't see much disagreement -- in more qualitative terms. The points of contention are really the weight he's putting behind them or the deduction/reasongin, which brought about one or many of his reasons -- see Marco's comment about deduction or Vince, faf's, Pana's ... disagreement with his quantities. Realise that they're not out right attacking the quality, they're targeting the quanties or the weights of the arguements.
Ultimately, your posts SEEM nothing more than ad hominem attacks, supported by fallacies. Though there is a large portion of people who disagree with deadmeat on the whole, I have yet to see an arguement posted against him by a reasonable poster which attacked the fashion in which he reasons.
The debate that takes place between the people on this board whom exercise to a formal or informal degree good reasoning and debate (principal of charity, abusing fallcies, etc ... ) rarely mirror your reasoning, save violence in some people's words -- *cough*Vince*cough* .
It basically works like this. Much like your previous post which is chalk full of sarcasm and pomp; it lacks any reasoning which is in anyway valuable to the discussion.
If one was to examing deadmeat's reasoning. One would say we disagree with his conclusion, nevertheless it's strong and well supported by the premises his presents.
Even the reasons he provides for his arguements don't see much disagreement -- in more qualitative terms. The points of contention are really the weight he's putting behind them or the deduction/reasongin, which brought about one or many of his reasons -- see Marco's comment about deduction or Vince, faf's, Pana's ... disagreement with his quantities. Realise that they're not out right attacking the quality, they're targeting the quanties or the weights of the arguements.
Ultimately, your posts SEEM nothing more than ad hominem attacks, supported by fallacies. Though there is a large portion of people who disagree with deadmeat on the whole, I have yet to see an arguement posted against him by a reasonable poster which attacked the fashion in which he reasons.
The debate that takes place between the people on this board whom exercise to a formal or informal degree good reasoning and debate (principal of charity, abusing fallcies, etc ... ) rarely mirror your reasoning, save violence in some people's words -- *cough*Vince*cough*
.DeadmeatGA
Banned
...
To nAo
Since it is known that IBM does not provide with any kind of auto parallelization technology(IBM's CELL program engineers admit they don't have it), this is the only way to deal with a beast like CELL, at least initially.
To Faf
To Megadrive
To nAo
Yea, but it is a lot easier to have those 8 VUs work on single system of linear equations than have them invididually FMAC through 8 different equations. Even running two identical 4x4 matrices side by side on same vector stream would be easier than running several different matrices in parallel.
Since it is known that IBM does not provide with any kind of auto parallelization technology(IBM's CELL program engineers admit they don't have it), this is the only way to deal with a beast like CELL, at least initially.
To Faf
For memory DMA only. No I/O stuffs. You have to go through Linux for that.
To Megadrive
I don't know if the VU2s are superscalar. There is no need for this.
4. Same as VU2s in CELL. VU1 does have one additional FDIV unit though...
DeadmeatGA
Banned
...
To Grall
To Saem
To Paul
Think about it, when the PSX2 was released in March 4th, 2000, the EE didn't pack in more transistors than top-end and workstation processors of time. The only bar Sony raised was the kind of chip that went into a console. Until now, all CPUs that went into consoles were substantially less powerful and smaller than contemporary workstation processors of time; Kutaragi Ken changed all this by putting in a chip as large as any of top end workstation chips; but SCEI couldn't pack in more.
The history tells us that SCEI will put in a fairly large chip into PSX3; it will be comparable, but will not exceed the transistor counts of contemporary workstation processors, because everybody's chip fabrication playing field is more or less level. And I do not know of any 65 nm fabricated CPUs that will have 500 million logic transistors; there are limits to what SCEI can actually fabricate.
To Grall
A words that better suits you than me.
To Saem
Thank you.
To Paul
Of course Sony can't, unless they invented some kind of vertical transistor packing technology which I am sure they didn't. There are limits to what Sony can put on each die and compromises are made, as evidenced by 12 MB eDRAM and R4000 cores of PSP.
Think about it, when the PSX2 was released in March 4th, 2000, the EE didn't pack in more transistors than top-end and workstation processors of time. The only bar Sony raised was the kind of chip that went into a console. Until now, all CPUs that went into consoles were substantially less powerful and smaller than contemporary workstation processors of time; Kutaragi Ken changed all this by putting in a chip as large as any of top end workstation chips; but SCEI couldn't pack in more.
The history tells us that SCEI will put in a fairly large chip into PSX3; it will be comparable, but will not exceed the transistor counts of contemporary workstation processors, because everybody's chip fabrication playing field is more or less level. And I do not know of any 65 nm fabricated CPUs that will have 500 million logic transistors; there are limits to what SCEI can actually fabricate.
Re: ...
Deadmeat, I just have one question. If STI does this, as they will, what are you going to do with yourself?
Also, will you stop comparing the PSP (which will be transistor heavy as it is) that has size, power, and thermal requirements to what STI is doing in Austin? This is insane.
Ohh, and one more thing to ponder you obscure and mysterious genius whose sheer intellect and vision of the world around him far surpasses the only other comparable man I can think of, Ramanujan - If SCE and Toshiba could do what they did (and you admit was an achievement concerning lithography) on the PS2's ICs... what's going to happen when you team them with the likes of IBM for 4 years on process development?
I fear for you in 2 years.
Deadmeat, I just have one question. If STI does this, as they will, what are you going to do with yourself?
Also, will you stop comparing the PSP (which will be transistor heavy as it is) that has size, power, and thermal requirements to what STI is doing in Austin? This is insane.
Ohh, and one more thing to ponder you obscure and mysterious genius whose sheer intellect and vision of the world around him far surpasses the only other comparable man I can think of, Ramanujan - If SCE and Toshiba could do what they did (and you admit was an achievement concerning lithography) on the PS2's ICs... what's going to happen when you team them with the likes of IBM for 4 years on process development?
I fear for you in 2 years.
Paul said:Yea and we all know you can't cram a ton of transistors on 0.65 micron
Of course Paul, I'm sure the PS3 will have a pretty interesting processor (EE2/CELL or whatver it's name), that said, nothing is free. They'll probably have to cut corners somewhere, just wonder how well they'll do. It sure looks to be an interesting beast to write code for, too bad I won't
MfA said:
This is debatable and 9-to-1, wrong. At even the most fundimental level we can state (as the Electronic Design Chain Article sets a timeline for) that the patent was filed after the primilinary work done by the STI contact teams.
Thus, unless you assume that they're ridiculously misguided - you must assume that the architecture they layed out (and SCE ultimatly patented) is designed around a target process, size, and preformance. So, very little should change in the grand scheme of things. Perhaps parts of thre microarchitecture will differ, but the macroscopic view will be very similar.
How could they have an 'exact plan'??
The engineers are inventing a new chip, you can not have a 1. 2. 3. 4.... step by step plan on what to do if you are designing something new.
Of course they are doing much research as they go, but that doesn't mean they don't have some general plan(s) and goal.
They are making that plan, for manufacuring the chip.
The engineers are inventing a new chip, you can not have a 1. 2. 3. 4.... step by step plan on what to do if you are designing something new.
Of course they are doing much research as they go, but that doesn't mean they don't have some general plan(s) and goal.
They are making that plan, for manufacuring the chip.
MfA said:
HOW?!
The message provided no links, no quotes and in fact no means of tracing the source of this "information" whatsoever.
Anyway, why the *bleep* should I do YOUR work? If you claim something, it's your job to back it up not mine.
Who are those engineers and where did they say there's no plan?
I keep wondering how so many here seem to have such precise information on the inner workings of Cell's design process, I find that very intriguing...
How do you know? Or is it perhaps that you really don't know, you're just guessing?Besides, you don't think these people are pretty good at hitting near-ish the mark they're aiming for? After all, the bulk of the design talent, at least from IBM, comes from their supercomputer division I heard someone here say. If true, it wouldn't be as if these guys haven't ever designed a complicated processor before or anything like that...
Not aiming this at anyone in particular, but if the sceptics of this forum REALLY are so smart and know so much better than the proven talents of Sony/IBM/Toshiba, how the funk is it that you guys are sitting on your asses typing forum posts instead of working at an IC design studio designing kickass processors for a living?
Either Cell will be like what's described in the patent, or it won't! Calling your speculation on what it will be anything OTHER than speculation is just silly. I don't claim to KNOW what's possible or not, unlike some other people (Deadmeat is just one such person, a person admitting to having no education on the subject I might add), yet you insist his fabrications have merit:
Uh, right...
This tells more of you than it does about me I'd say.
*G*
Panajev2001a
Veteran
About the 65 nm manufacturing process is concerned and the CELL chip, when I see Toshiba stating that the new Oita #2 plant's 65 nm lines are going to be built in such a way to make the upgrade to 45 nm technology "smoother" and he comments do quite suggest that the 45 nm node for them is not that far ahead... I can think about that, I can think about the Broadband Engine.
This chip will push the 65 nm process quite a bit and the die size will not be ultra small ( which is not bad for good heat dissipation ) instead I am expecting quite a big chip ( in the orders of 280 mm^2 or more: this is after all the size of the GS in its initial incarnation and the GS was not manufactured on 300 mm wafers while CELL chips will be using 300 mm wafers ).
Economically it will hit SCE, but that will not be a long term problem: they will have to hold strong in the first Quarter after the launch of the console.
With mass production of Oita #2 starting around mid 2004 and Nagasaki #2 that will add even more 65 nm CELL production capacity, yelds should not be horrible by mid 2005 ( estimated PlayStation 3 launch date ) and if they can get to manufacture a good volume of chips per month the losses will be a bit easier to take.
By Q4 2005 and Q1 2006 yelds should have improoved on both Oita #2 and Nagasaki #2 65 nm lines and volume production would be positively affected: they would not only have more working chips per wafer, but they will have increased the number of wafers per month that they can work on.
I expect by Q2 or Q3 2006 to see that Oita #1 ( the part co-financed by SCE ) and Nagasaki #1 to have their lines upgraded to 65 nm from the actual 90-130 nm: they would likely keep the 90 nm lines for the EE+GS@90 nm and the PSP chip until those two are shrinked to 65 nm as well and upgrade the other sections to 65 nm ( one floor used for 90 nm production and another floor used for 65 nm production ).
SCE is moving to China current PlayStation 2 production and will basically keep in Japan only the 90 nm lines related to PSX, the EE+GS@90 nm and the PSP.
By Q4 2006 we should have basically all 4 fabs working on CELL chips ( CELL will be used in a lot of Sony corp. products as already stated by Sony executives in numerous occasions ).
By that date I expect a 45 nm die shrink of the Broadband Engine to be in place at SCE and Toshiba R&D labs and by Q1 2007 they might have done some nice work on Oita #2 and Nagasaki #2 lines transitioning the 65 nm lines to 45 nm.
The 45 nm die shrink ( which involves some internal redesign and renewed and optimized transistor's layout ) will allow to cut the cost quite nicely as it will allow to reduce the area of the chip to 55-60% ( or less ).
By this date, with better yelds, with the production volume ue to 4 fabs producing 65 nm Broadband Engines processors, the costs of producing these chips should have already decreased quite a bit already allowing SCE to reduce the loss taken on each PlayStation 3 sold by a non trivial amount.
This chip will push the 65 nm process quite a bit and the die size will not be ultra small ( which is not bad for good heat dissipation ) instead I am expecting quite a big chip ( in the orders of 280 mm^2 or more: this is after all the size of the GS in its initial incarnation and the GS was not manufactured on 300 mm wafers while CELL chips will be using 300 mm wafers ).
Economically it will hit SCE, but that will not be a long term problem: they will have to hold strong in the first Quarter after the launch of the console.
With mass production of Oita #2 starting around mid 2004 and Nagasaki #2 that will add even more 65 nm CELL production capacity, yelds should not be horrible by mid 2005 ( estimated PlayStation 3 launch date ) and if they can get to manufacture a good volume of chips per month the losses will be a bit easier to take.
By Q4 2005 and Q1 2006 yelds should have improoved on both Oita #2 and Nagasaki #2 65 nm lines and volume production would be positively affected: they would not only have more working chips per wafer, but they will have increased the number of wafers per month that they can work on.
I expect by Q2 or Q3 2006 to see that Oita #1 ( the part co-financed by SCE ) and Nagasaki #1 to have their lines upgraded to 65 nm from the actual 90-130 nm: they would likely keep the 90 nm lines for the EE+GS@90 nm and the PSP chip until those two are shrinked to 65 nm as well and upgrade the other sections to 65 nm ( one floor used for 90 nm production and another floor used for 65 nm production ).
SCE is moving to China current PlayStation 2 production and will basically keep in Japan only the 90 nm lines related to PSX, the EE+GS@90 nm and the PSP.
By Q4 2006 we should have basically all 4 fabs working on CELL chips ( CELL will be used in a lot of Sony corp. products as already stated by Sony executives in numerous occasions ).
By that date I expect a 45 nm die shrink of the Broadband Engine to be in place at SCE and Toshiba R&D labs and by Q1 2007 they might have done some nice work on Oita #2 and Nagasaki #2 lines transitioning the 65 nm lines to 45 nm.
The 45 nm die shrink ( which involves some internal redesign and renewed and optimized transistor's layout ) will allow to cut the cost quite nicely as it will allow to reduce the area of the chip to 55-60% ( or less ).
By this date, with better yelds, with the production volume ue to 4 fabs producing 65 nm Broadband Engines processors, the costs of producing these chips should have already decreased quite a bit already allowing SCE to reduce the loss taken on each PlayStation 3 sold by a non trivial amount.
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