Why a daughter die?

If they're using the NEC edram it's probably 500mhz.

 

IIRC GS had a 2560-bit bus or around there.

 

yep 2560-bit bus -

wasn't it something like 1024-bit read, 1024-bit write, 512-bit for texture ?

 

Don't forget that ms can now take advantage of processes .


Edram is much denser and sometimes a process is certified for edram and sometimes its not . So while they wait for that process to be certifed or be capable of edram production , they can still drop the parent die to the smaller micron process and reap better yields on half the chip while they wait to drop the edram micron process

So in the future u may see the parent die at 65nm and the edram at 90nm . Then the parent die at 45nm and the edram at 65nm

 

Not a good reason. It's not difficult to have multiple clocks with a single die. I refer to recent Nvidia talk for proof.

 

The two have nothing in common. All shader processing is done on the parent die.

 

I said this a few posts later.

Jawed

 

EDIT!!!!

now I'm confused... from dave's article it said its 500 Mhz but from this article it said 2 Ghz :?

can anyone clarify???



from this one...
http://www.beyond3d.com/forum/viewtopic.php?p=528585

quote from Dave's article...
http://www.beyond3d.com/articles/xenos/index.php?p=02

 

well if clocked at 500Mhz then there is a 4096 bit connection between duaghter die and the edram it self to give the 256 GB/s BW. while there is a 512 bit interface between the parent die and the daughter die to give the 32 GB/s.

 

Sounds good. Looks like 500 MHz uniform clock throughout.

 

dave was right all along!!!

how foolish of me to doubt him

 

QDR...

 

this topic name is pretty depressing