Trident's new DX8.1 3D Graphics Processor for laptops

It interesting that it sounds as though UMC and Trident have got .13um up an running. ATi already have a working reltionship with UMC so I wonder if we are going to see ATi .13um procducts soon?
 
the highest 3D performance at 1 billion pixels/sec and 8 billion texels/sec.

Hands up those who think that those texels are indeed just texels, as in 8 texels for trilinear, indicating the part does 1 clock trilinear filtering... :eek:
 
Kristof said:
the highest 3D performance at 1 billion pixels/sec and 8 billion texels/sec.

Hands up those who think that those texels are indeed just texels, as in 8 texels for trilinear, indicating the part does 1 clock trilinear filtering... :eek:
Seems likely, however I think if that's the case more than 10GB/s bandwidth is just overkill.

Another possibility would be that each of these TMUs is just bilinear capable, so trilinear filtering needs two TMUs...
 
I can't imagine how a chip having both pixel and vertex shaders is only 30 million transistors. I have a gut feeling that there is no hardware vertex shaders on this chip much like on the SiS DX 8 card. Maybe they only have one set of registers for all the different functions. It would be a very intensive task to program for in ASM, but having fewer registers would surely limit the amount of transistors.
 
I think it is hilarious that Dave Salvador write an article saying it is DX9 when the press release clearly says DX8.1 (and to what level, no one every says, kinda like SiS has been). The 30 million transistors has me puzzled since the Radeon 8500 has over 60 right?
 
Trident gave texel fetch rate when announced BladeXP, so I think they do that again. Anyway I would welcome an 1GPixels/s and 2 GTexels/s cheap DX8 chip too.

And I really doubt they use TBR the same way PowerVR does, since the PR just mention improved memory controller, but not a single word about rendering only visible pixels. I guess they managed to improve cache efficiency with the new memory controller.
 
Does anyone know how the framebuffers is laid out in memory on other chipsets ?

I would guess they would be optimized for spatial locality (in 4x4, 8x8 or whatever x whatever chunks), and hence with cache, most chipsets today could be called "tilers"

Cheers
Gubbi
 
Gubbi said:
Does anyone know how the framebuffers is laid out in memory on other chipsets ?
I would guess they would be optimized for spatial locality (in 4x4, 8x8 or whatever x whatever chunks), and hence with cache, most chipsets today could be called "tilers"
GF3/4 do support tiled framebuffers (several arrangements) and zbuffers (8x4, 4x4).
I guess you're right, almost every GPU could be called tiler, with this particular meaning.

ciao,
Marco
 
The only claimed fact that could still make me think of it being a Tiler is the low transistor count.

As far as the 32TMU's claim or more specific 8 TMU's per pipe, could it be someone reporting rumours got confused with let's say 8 textures per pass (multitexturing) that it could have gotten to that exaggeration?

In any other case could someone explain what good would nowadays 8TMU's per pipe do? (TBR or IMR).
 
Nappe1 said:
darkblu said:
Nappe1 said:
This was great news until I heard something that made me climb to ceiling...

umm... let's see... I need something very special to celebrate this... yep. Champagne... definately.

/me goes to nearest ALKO.

with what pricetag?

Champagne is never cheap. or did you mean those news? those news were pretty cheap... costed to me almost nothing. ;)

no, i actually meant the price tag in that news ;)
 
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