Toms Hardware: GeForce 5200 is 2x2?

But this definition has its problem.
For example, NV2X has four Z test units per pixel pipeline. That is, a GF3/GF4 can fetch and test 16 Z values per cycle. Does that make GF3/GF4 "16 zixels per cycle?" I don't think it fit the discussions here.

So I think it's better to use "Z/stencil writes per cycle" than "zixels."

 

You will just have to look to fillrate test result 2 second to see that 5200 is 4x1, not 2x2.

 

Well NV25 can write 16 z-values per clock, if it's doing 4xMSAA. (Where "write" has a nonliteral definition due to z-compression.)

On the other hand, if I understand the definition of "fragment" correctly, when you're doing e.g. 4xMSAA you have 4 sub-pixels but still only one fragment. In other words, NV25 can write up to 16 z-values per clock, but they are associated with at most 4 fragments. If so, we can save my definition by adding one letter:

"the z/stencil values associated with a particular fragment"

Or is there a better way of saying it?

 

Ugh! My understanding of fragment was that if you're doing 4xMSAA you have 4 fragments and one pixel :?

 

<speaking to the air> "shixel" sounds like a "definitely profane English term"...if I were to rename "proxels" I'd call them something like "Ixel" (for instruction element, maybe "Iixel" to prevent confusion with a pixel typo), "Cixel", or drop the "h" in "shixel". Or maybe just add a letter in front of "pixel" (I-pixels, Z-pixels, etc).

Hmm...just realized "sixel" is a bit close to "sexel", and, my god, that term could sell a LOT of cards.... . Maybe it would be safer to keep that term away from marketroids...

Maybe Opsel or O-pixel would be safer?

 

Well, i think Marc know what he is talking about since he is the webmaster @ http://www.hardware.fr/ (and probably has a card )

 

I like shiznixel. It would really bring 3d technology to the urban youth.

 

End of the NDA on monday, isn't it?

 

So I expect the NV35 launch party will be headlined by Snoop Dogg?

Of course, GeForceDMX has a nice ring to it...

 

Nv30=4*2+8z
Nv31=4*1+4z
Nv34=2*2+2z

No that can´t be right or?

 

Much better than GeForceFX at any rate.

 

No. I looked it up (in the OpenGL spec): four samples, one fragment. The best way to describe the difference between a fragment and a pixel is that "pixel" refers to an area of the finished frame (or to a slot in the framebuffer if you'd rather look at it that way), whereas "fragement" refers to a pixel-sized object making its way through the rasterization pipeline.

 

my investigations show that

NV31 is

4х1 in blend stages only
2х2 on all p shaders with 2 stage ALUs per pipe probably
all commands on same ALU's - so 1.1 and 1.4 and 2.0 speed equal
its NV35 approach

NV34 is true half of NV30 in terms of pixel pipes organisation

2х2 always.
1.4 and 2.0 twice slower like in NV30

 

What do you mean by "blend stages only"? Fixed-function, i.e. not shaders?

I wonder why the TMUs would be limited to 2x2 during shader programs but 4x1 otherwise. How exactly are you testing this, anyways?

Anyways, interesting stuff; and here's hoping your description of NV35 is on target.

 

The nVidia video yesterday mentioned that the nv31 "barrowed" from the nv35, ie Intellisampe 2.0. I wonder if this is just another way of saying they finaly incorporated all commands onto the same pipe for the nv31 and nv35. My guess is that would also save them transistors of the nv30 design.

Wow, a 2x2 architecture huh? Looks like we're still going backwards. nVidia was the first to market a 4x1 design in what, 99' with the GeForce256. Here we are 3 years later going back to a 2x2 desing. Sheesh.

 

yep 4х1 - it's "no pshader" cases (register combiners).

limited becouse in shader program we always deal with more than one command so no worry about less pipes if they more powerful.

i think nv31 have 4 universal alu's at all. we can use it as 2 stage 2х2 or one stage on 4х1. for hard texturing seems they can get some optimisations from 2 stage 2 tmu scheme so they use it.

rule simply - deeper pipe - probably lower fetch latency from one command standpoint.

yep, seems that nv35 will have pretty same pipes behaviour

 

yep i talk about this saving a less than week ago here - if we do 2 universal FP/int stages on each pipe we probably dont save to much but dont pay to much also. and get ability to fetch textures in paralel with ps20
so they save from case where they simply add another one fp ALU to nv30 but count of copmlexity increase in this case also a bit

nv10 have 4х1 _or_ 2х2 design

same as here. no somthing new to nv in having flexible configured pipes

PS - i use RightMark 3D synthetic tools for measuring pixel and texel fillrate in different modes with different counts of textures used.

It's our own synthetic tests set that enables very focused investigation of different GPU blocks

 

I've done a little PS2 test program and sent it to someone who got a FX5600 Ultra ( not going to say the name, because I'm not 100% sure nVidia authorizes to give this type of number before the 10th... )
The program does about 20 arithmetic instructions, and 1 texture instruction.
It then draws the screen three times, without a Z buffer, and with a 128x128 texure ( screen resolution: 1024x768 )

The result he gave me was 14FPS ( using FRAPS )

So, considering a margin or error, I'd consider 700MIPS ( global instructions, that is )

And the clock rate of the FX5600 Ultra is 350

So... 700/350 = 2
2 Global Instructions/clock?


Uttar