The LAST R600 Rumours & Speculation Thread

[Geo]

What's your gut feeling on the R600? In particular, is it going to be faster than the G80 and G81?

I'm sensing that it will slightly edge out G80, but G81 will easily beat it while using less power.

Do you have any solid reason to believe that a hypothetical G81 is going to close the bw deficit (as opposed to marginally narrow)? I don't. So I think such a scenario, should it come to pass, could have variable results across different settings. We'll have to see first with R600 exactly how far up the resolution/settings food chain you have to go for the bw advantage to start to shine.

Edit: Of course, having said that, looking at that ROP/memory implementation they did, I don't see any particular theoretical challenge for them to step up to 512-bit if they are willing to spend the silicon. It's obviously modular, as GTS attests. But are they willing? And at what process will they refresh: 90, 80, or 65 --and the implications for timing.

 

[INKster]

Do you have any solid reason to believe that a hypothetical G81 is going to close the bw deficit (as opposed to marginally narrow)? I don't. So I think such a scenario, should it come to pass, could have variable results across different settings. We'll have to see first with R600 exactly how far up the resolution/settings food chain you have to go for the bw advantage to start to shine.

G80 is not exactly starving for BW at the moment.
So, unless real world conditions and software demand much more in the near future, i think the whole 384bit vs 512bit debate is a moot point.

By the time a 512bit bus + GDDR4 combination is truly useful, both IHV's will be using it anyway...

 

[icecold1983]

is the g80 even bandwidth limited? i would think its more limited by the core than the memory.

 

[Geo]

is the g80 even bandwidth limited? i would think its more limited by the core than the memory.

I believe those scenarios exist, yes. Whether its "more" or not probably depends on the scenario.

 

[Natoma]

Think HDR+High AA/AF+High Res.

Bandwidth would get swallowed rather quickly. What geo is positing is, how quickly. If there's a noticeable difference at 1600x1200, then big win for ATI. If it takes going to 2048 res or higher, not so much.

 

[nonamer]

Do you have any solid reason to believe that a hypothetical G81 is going to close the bw deficit (as opposed to marginally narrow)? I don't. So I think such a scenario, should it come to pass, could have variable results across different settings. We'll have to see first with R600 exactly how far up the resolution/settings food chain you have to go for the bw advantage to start to shine.

Edit: Of course, having said that, looking at that ROP/memory implementation they did, I don't see any particular theoretical challenge for them to step up to 512-bit if they are willing to spend the silicon. It's obviously modular, as GTS attests. But are they willing? And at what process will they refresh: 90, 80, or 65 --and the implications for timing.

It's a gut feeling. All the delays, need for a newer process and enormous power consumption sounds like not everything is right with the R600.

 

[Arty]

G80 is not exactly starving for BW at the moment.
So, unless real world conditions and software demand much more in the near future, i think the whole 384bit vs 512bit debate is a moot point.

By the time a 512bit bus + GDDR4 combination is truly useful, both IHV's will be using it anyway...

You came to the conclusion that 512b isnt that useful even before it was launched?

 

[Geo]

As I've said before, it puzzles me that people would think that AMD would do 512-bit for just a checkbox. But it *really* puzzles me why people would think that AMD would do 512-bit *and* GDDR4 for just a checkbox.

 

[KimB]

As I've said before, it puzzles me that people would think that AMD would do 512-bit for just a checkbox. But it *really* puzzles me why people would think that AMD would do 512-bit *and* GDDR4 for just a checkbox.

Oh, I'm sure they didn't. But that doesn't necessarily mean that it won't end up being just that, at least for now.

 

[Natoma]

Given the engineering difficulty of producing a 512bit bus? I'd say it definitely means that. It's just too damn expensive and would make no sense unless the planning was there to build significant capabilities into the core to utilize that bandwidth.

An external 512bit bus isn't the same thing as the 512bit ring bus experimentation during R5xx.

 

[KimB]

Given the engineering difficulty of producing a 512bit bus? I'd say it definitely means that. It's just too damn expensive and would make no sense unless the planning was there to build significant capabilities into the core to utilize that bandwidth.

An external 512bit bus isn't the same thing as the 512bit ring bus experimentation during R5xx.

Except that the decision had to be made quite some time ago, and any misreading of the CPU or 3D games markets might cause them to overshoot the required bandwidth.

 

[Natoma]

We've already seen from past iterations that when it comes to external bandwidth, ATI/AMD has been spot on with their requirements and building balanced parts.

 

[Razor1]

We've already seen from past iterations that when it comes to external bandwidth, ATI/AMD has been spot on with their requirements and building balanced parts.

and the r520 showed that?

 

[Natoma]

and the r520 showed that?

We've already seen from past iterations that when it comes to external bandwidth, ATI/AMD has been spot on with their requirements and building balanced parts.

There's a reason why I added the word external.

Also,

Given the engineering difficulty of producing a 512bit bus? I'd say it definitely means that. It's just too damn expensive and would make no sense unless the planning was there to build significant capabilities into the core to utilize that bandwidth.

An external 512bit bus isn't the same thing as the 512bit ring bus experimentation during R5xx.

 

[Razor1]

ah I see :smile:

 

[CJ]

One source suggested that the editor/press launch event for R600 is actually not at Cebit but a few days earlier on the 12-13th of March. Supposedly no benchmarks will be released to the public because the NDA will be lifted 2 weeks later at the end of March. Yes, this all sounds a bit weird, but it's just what I heard. And to top it off, it seems that AMD is being very secretive about it so dates could be shuffled around again at the last moment.
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[Tim Murray]

I think it should just be called the FX2900.

*runs away*

Oh Bob, you card.

Also, Natoma, aren't you only basing that on R300? There hasn't been a significant jump in bandwidth since then.

 

[Natoma]

Not particularly. I would think the bandwidth increases from R3xx (~23GB max) --> R4xx (~38GB max) --> R5xx (~64GB max) have been rather significant.

 

[Tim Murray]

Not particularly. I would think the bandwidth increases from R3xx (~23GB max) --> R4xx (~38GB max) --> R5xx (~64GB max) have been rather significant.

I think that's more a factor of the DRAM market than anything ATI consciously did, though. Also, wasn't the limited availability of the X800 XT PE blamed at least in part on the ability of Samsung to supply 1.6ns GDDR3?

 

[dizietsma]

Surely the AIB partners would want to show it off at cebit so the announcement should be just before and then sales slightly after, that would seem the most logical. If they do not lift NDA before cebit then the guys on the Sapphire and HIS stands might just be sitting there watching XFS etc displaying mid range G8 series cards and possibly G81 !

At this rate the K8L will be out first