The LAST R600 Rumours & Speculation Thread

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As I've said before, it puzzles me that people would think that AMD would do 512-bit for just a checkbox. But it *really* puzzles me why people would think that AMD would do 512-bit *and* GDDR4 for just a checkbox.

Just an idea. If their chip is less modular then G80 they might have decided to go directly for 512/1024 Ringbus insted of going 384/768. Or if they wanted the 1GB RAM sticker in their box.

Or they were just surprised that NV did go for the in-between solution.

There are many possible reasons and not all would indicate that they need 512bit-Bus or that it will give R600 a significant edge.
 
As I've said before, it puzzles me that people would think that AMD would do 512-bit for just a checkbox. But it *really* puzzles me why people would think that AMD would do 512-bit *and* GDDR4 for just a checkbox.
I don't think anyone is suggesting that. But just because the designers had a good reason for including a 512-bit bus in the design that doesn't necessarily mean that it will be useful in real-life. Designers make mistakes sometimes.

By way of a counter-example, think about Intel's "Netburst" CPU architecture. It has a 31-stage pipeline. Now, before it launched, everyone could have been sitting around speculating that the chips were going to overclock all the way to 10GHz, and saying "if the chips can't clock that high, why would Intel have made the pipeline so long? They would hardly have done it just as a checkbox feature, would they? There must be a reason why it's 31 stages. And apart from insane clock speeds, what else could it be?"

There was, in fact, a very good reason why the pipeline was that long: Intel genuinely intended that the architecture (after a couple of process shrinks) would ultimately go all the way up to 10GHz. However, once they actually had the chips in production and started to ramp the speeds up, they hit a problem: the chip was less energy-efficient than they'd anticipated, and, in particular, process shrinks had far less of an impact on heat-production than they'd expected. So, while Netburst chips can, in fact, hit 8GHz or higher with off-the-scale custom cooling solutions in the laboratory, in normal use they were never going to get anywhere near that, because they ran too hot.

This meant that the official clock-speeds never got anywhere near what Intel had originally intended, and the 31-stage pipeline was therefore (with hindsight) totally useless. However, by the time everyone had realised this, Intel was already committed to the Netburst design and it was too late to do anything about it.

Given that R600 is at least six months late (or will be by the time it launches) ATI has clearly encountered significant problems of some kind, which may or may not have been entirely resolved. Either way, it is perfectly possible that, if R600 had worked as ATI originally envisaged, the 512-bit bus would have been immensely useful, but that, in real life, the bandwidth been rendered pointless because of practical limitations that the ATI engineers didn't anticipate (in the same way as the Netburst pipeline depth was rendered pointless by problems the Intel engineers didn't anticipate).

I'm not saying this is what has happened; but it's a possibility. It's quite right to say that ATI would not have included a 512-bit bus just for the hell of it; they must have had what seemed like a very good reason at the time. But it is wrong to assume that this decision must turn out to be correct, even with the benefit of hindsight. Engineers make mistakes sometimes.
 
If they were designing to use all of that bandwidth and we know the approximate size of the chip, 32 TMUs, and ~800MHz clocks then it seems fairly obviously the ALUs are running double the core clock. It's the only logical way I can think of to balance out the chip. It doesn't necessarily mean they have them running that fast but it seems a likely goal.

They never needed that kind of shading power before so I'm not aware of any attempts to ramp up the clockspeed on the ALUs. It very easily could have been the TMUs and ROPs holding back the speeds before. Were G80's clock gains simply from going scalar, double-clocking the ALUs, or more likely a combination of both. Given the difference in processes, ALUs running at ~1.6GHz doesn't seem to unreasonable. Plus it's in line with all the strange clockspeed rumors that keep coming out.

I'm also becoming convinced that with the amount of chips Nvidia seems to be ordering they're planning a GX2 style chip with G81. If that's the case they're anticipating R600 being almost twice the speed. Which is inline with the bandwidth figures we have.
 
If they were designing to use all of that bandwidth and we know the approximate size of the chip, 32 TMUs, and ~800MHz clocks then it seems fairly obviously the ALUs are running double the core clock. It's the only logical way I can think of to balance out the chip. It doesn't necessarily mean they have them running that fast but it seems a likely goal.
Umh..can't see any logic in this statement, can you elaborate on that?
 
I'm not saying this is what has happened; but it's a possibility. It's quite right to say that ATI would not have included a 512-bit bus just for the hell of it; they must have had what seemed like a very good reason at the time. But it is wrong to assume that this decision must turn out to be correct, even with the benefit of hindsight. Engineers make mistakes sometimes.

Ah, so no one's arguing from a "well, nvidia didn't do it, therefore it must not be the thing to do" internal rationale then? It's just all "well, AMD probably screwed up"?

While both are possibilities, they do not strike me as the mainline. Occams razor and all that. G80 was several months late as well --I don't recall anyone arguing it was probably broke based on that.
 
G80 was several months late as well --I don't recall anyone arguing it was probably broke based on that.

But in case of G80 there was no pressure to release whatsoever, so they could afford being "late". In case of ATI, every day of delay is loads of lost revenues and damage to the company's image.

That is, unless R600 turns out being the product they would have if they skipped one cycle completely, which I personally doubt.
 
G80 was several months late as well --I don't recall anyone arguing it was probably broke based on that.
Well, R600 is several months later than G80. :) They were supposed to ship at the same time.

More to the point, there weren't any bizarre and inexplicable facts known about G80 prior to its launch - nothing comparable to R600 having a 512-bit bus, anyway. You don't recall arguments like this because there wasn't anything comparable to speculate about.

The delay is actually only of secondary importance. The point I'm making is simply:

1) Clearly ATI's engineers must have had what they thought was a very good reason to include a 512-bit bus.

2) The fact that they thought they had a very good reason does not automatically imply that they were right. Engineers of all sorts (ATI, AMD, Nvidia, Intel and everybody else) have been known to make bad decisions from time to time.

You mentioned Occam's razor; possibly the best way to apply that here is to say "if no one can come up with a single reasonable explanation as to what all that memory bandwidth is going to be used for, the simplest possible explanation is that it won't be used for anything." It must have been intended to be used for something, but that doesn't preclude the possibility that it won't actually be used for anything in the real world. (See also Netburst pipeline).
 
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But in case of G80 there was no pressure to release whatsoever, so they could afford being "late". In case of ATI, every day of delay is loads of lost revenues and damage to the company's image.

Help me with the logic of that as to how it applies to the point I made? "Affording" being late has what to do with engineering and architecture issues? The only thing I can come up with is that its broke and they can't afford to take the time to fix it? Except then if they weren't taking the time, then why are they late? That's circular. So we're back to "if it's late then it must be broke", and that's just not true. The history of video cards is most of them are "late" to one degree or another, and relatively few of them are broke when they finally do arrive. It happens, but not often.
 
Well, R600 is several months later than G80. :) They were supposed to ship at the same time.
Early rumors (2005) put R600 after G80 not at the same time.

The point I'm making is simply:

1) Clearly ATI's engineers must have had what they thought was a very good reason to include a 512-bit bus.

2) The fact that they thought they had a very good reason does not automatically imply that they were right. Engineers of all sorts (ATI, AMD, Nvidia, Intel and everybody else) have been known to make bad decisions from time to time.
On the flip side it does not automatically mean we start discounting 512b until Nvidia gets it. :D
 
More to the point, there weren't any bizarre and inexplicable facts known about G80 prior to its launch - nothing comparable to R600 having a 512-bit bus, anyway. You don't recall arguments like this because there wasn't anything comparable to speculate about.

Apart from the crazy (up to) 1.5 Ghz clock and 384-bit bus claims that next to no one beleived you mean? :D
 
Help me with the logic of that as to how it applies to the point I made?

It's a different context and sum of circumstances IMO.

"Affording" being late has what to do with engineering and architecture issues? The only thing I can come up with is that its broke and they can't afford to take the time to fix it?

Lots. For example, you'll take some extra time to tweak things or try stuff out because you simply can, having no pressure from the competition. After all, nV released NV40 with faulty PureVideo because they wanted to get it out - is this a valid example?

So we're back to "if it's late then it must be broke", and that's just not true.

Never argued that at all, just the possibility is always there, regardless of which company we're talking about.
 
After all, nV released NV40 with faulty PureVideo because they wanted to get it out - is this a valid example?

I'd argue that's a case of being slightly broke for the sake of *not* being late. It's "late *and* broke" we're talking about here (and, sure, there are a few examples of that too. . .just not many).

Never argued that at all, just the possibility is always there, regardless of which company we're talking about.

True enough. :smile:
 
By way of a counter-example, think about Intel's "Netburst" CPU architecture. It has a 31-stage pipeline. Now, before it launched, everyone could have been sitting around speculating that the chips were going to overclock all the way to 10GHz, and saying "if the chips can't clock that high, why would Intel have made the pipeline so long? They would hardly have done it just as a checkbox feature, would they? There must be a reason why it's 31 stages. And apart from insane clock speeds, what else could it be?"

There was, in fact, a very good reason why the pipeline was that long: Intel genuinely intended that the architecture (after a couple of process shrinks) would ultimately go all the way up to 10GHz. However, once they actually had the chips in production and started to ramp the speeds up, they hit a problem: the chip was less energy-efficient than they'd anticipated, and, in particular, process shrinks had far less of an impact on heat-production than they'd expected. So, while Netburst chips can, in fact, hit 8GHz or higher with off-the-scale custom cooling solutions in the laboratory, in normal use they were never going to get anywhere near that, because they ran too hot.

This meant that the official clock-speeds never got anywhere near what Intel had originally intended, and the 31-stage pipeline was therefore (with hindsight) totally useless. However, by the time everyone had realised this, Intel was already committed to the Netburst design and it was too late to do anything about it.
.

a few corrections : the netburst architecture was to be in three major steps.
first, there were 20 pipeline stages (the 180nm and 130nm versions), then 31 stages (the prescott), then there would have been the Tejas on 65nm.. and the reason it was cancelled is simple : according to wikipedia it's netburst with 45 pipeline stages :oops:
 
It's "late *and* broke" we're talking about here

Well, 'late' *could* be a consequence of something being "broke" :)

Though I rather think they tweaked some stuff to remain competitive with the G81 or whatever the name turns out to be.
 
Well, 'late' *could* be a consequence of something being "broke" :)

Not impossible, but now we're back to my original point. . usually stuff is late so it won't be broke. :smile: Why pay the price of lateness if you don't get the benefit of not-brokeness? (unless you're a particularly ugly example that happens on rare occassions, but I really don't see any reason yet to go there)
 
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