Suzuoki's CELL Patent application revisited....
- Thread starter DeadmeatGA
- Start date
Panajev2001a
Veteran
Deadmeat, sorry for interrupting you, but you missed a step 
7.5: Interrupt
Seriously, I know you know few things, I just disagree with your conlusions as they are quite biased with lots of "Sony hate".
Just tone it down: they did not murder your family and slamming a console almost 2 full years before it is released is really annoying.
Annoying is also your constant whining about how you are "educating the ignorant masses" and how you "know so much more than everybody else" ( so you have your own graphics engine that betters Fafalada's one which has been shown to the public ? ).
7.5: Interrupt
Seriously, I know you know few things, I just disagree with your conlusions as they are quite biased with lots of "Sony hate".
Just tone it down: they did not murder your family and slamming a console almost 2 full years before it is released is really annoying.
Annoying is also your constant whining about how you are "educating the ignorant masses" and how you "know so much more than everybody else" ( so you have your own graphics engine that betters Fafalada's one which has been shown to the public ? ).
Re: ...
I believe the size of the chip (especially eDRAM) varies depending on fast it is clocked. There was an old thread about this. Panajev, can you dig it up , please? Anyhow, it's not like the Cell is set in stone, so S/I/T could change things around or improve things to make it reasonably sized. I am in agreement that it'll be big, but not necessarily impossible. It may be that they sacrifice speed for practicality.
It could go something like 4Ghz, but heat and cost would shoot so high that I doubt it could be done. So I agree.
Grall, it's not a CPU, it's 4 of them really with a lot of other stuff added on like the APUs and eDRAM. Mainly, it's going to be the power dissapation that going to stop the thing from going full speed.
In line with my prediction that PS3 will launch in late 2005 at the earliest.
DeadmeatGA said:
I believe the size of the chip (especially eDRAM) varies depending on fast it is clocked. There was an old thread about this. Panajev, can you dig it up , please? Anyhow, it's not like the Cell is set in stone, so S/I/T could change things around or improve things to make it reasonably sized. I am in agreement that it'll be big, but not necessarily impossible. It may be that they sacrifice speed for practicality.
It could go something like 4Ghz, but heat and cost would shoot so high that I doubt it could be done. So I agree.
Grall, it's not a CPU, it's 4 of them really with a lot of other stuff added on like the APUs and eDRAM. Mainly, it's going to be the power dissapation that going to stop the thing from going full speed.
[/quote]
In line with my prediction that PS3 will launch in late 2005 at the earliest.
Re: ...
AMD can't ramp SOI (or only slowly), IBM has only produced limited number of ICs with it. It still seems very much a boutique technology. There also seems to be problems with low-k dielectrics (IBM abandoning Silk, TSMC also postpones the introduction of low-k).
It's an awful lot of things that can go wrong. Sony better have a backup design for bulk Si if they are going to be sure to launch on schedule. This of course means at a lower performance point.
Cheers
Gubbi
Vince said:
AMD can't ramp SOI (or only slowly), IBM has only produced limited number of ICs with it. It still seems very much a boutique technology. There also seems to be problems with low-k dielectrics (IBM abandoning Silk, TSMC also postpones the introduction of low-k).
It's an awful lot of things that can go wrong. Sony better have a backup design for bulk Si if they are going to be sure to launch on schedule. This of course means at a lower performance point.
Cheers
Gubbi
Re: ...
They also have another year and a half to go. By then IBM will have had the Power4/5, PPC970, AMD's entire xHammer line up all on SOI. Infact, AMD Desden should be fully SOI soon. How is it boutique? IBM doesn't design any major part without it at this time AFAIK. The ~3X reduction in power is too big to pass up.
As for Low-K dielectrics, it'll be sorted out by then. Most people should have it sorted out by the 65nm node.
http://www.reed-electronics.com/ele...=article&articleid=CA303813&rid=0&rme=0&cfd=1
They also have another year and a half to go. By then IBM will have had the Power4/5, PPC970, AMD's entire xHammer line up all on SOI. Infact, AMD Desden should be fully SOI soon. How is it boutique? IBM doesn't design any major part without it at this time AFAIK. The ~3X reduction in power is too big to pass up.
IBM praised for PowerPC on SOI process said:
As for Low-K dielectrics, it'll be sorted out by then. Most people should have it sorted out by the 65nm node.
http://www.reed-electronics.com/ele...=article&articleid=CA303813&rid=0&rme=0&cfd=1
Panajev2001a
Veteran
In the past SCE has been conservatives with their initial specs: we had a 250 MHz EE and probably a 125 MHz GS.
Their final chips had 300 MHz ( EE ) and 150 MHz ( GS ) respectively.
I am quite positive that they will not announce certain specs and then back down from them.
Sony has been working with SOI for a while ( it licensed IBM's SOI process quite a while ago ) and they have been using IBM's help ( direct and indirect [through patent licensing] ) when working with CMOS5 ( 65 nm ) and CMOS6 ( 45 nm ).
In all their reports IBM engineers, SCE engineers and Toshiba engineers have been saying that CELL is coming along very nicely ( it is on schedule ) and by now they should have had already a clear idea of the final spec they target for and they should be hard at work on the final 65 nm silicon implementation of those specs ( expect a large die ) and on CELL software ( CELL OS and CELL programming APIs ).
Their final chips had 300 MHz ( EE ) and 150 MHz ( GS ) respectively.
I am quite positive that they will not announce certain specs and then back down from them.
Sony has been working with SOI for a while ( it licensed IBM's SOI process quite a while ago ) and they have been using IBM's help ( direct and indirect [through patent licensing] ) when working with CMOS5 ( 65 nm ) and CMOS6 ( 45 nm ).
In all their reports IBM engineers, SCE engineers and Toshiba engineers have been saying that CELL is coming along very nicely ( it is on schedule ) and by now they should have had already a clear idea of the final spec they target for and they should be hard at work on the final 65 nm silicon implementation of those specs ( expect a large die ) and on CELL software ( CELL OS and CELL programming APIs ).
