So why isn't Xenos 65nm yet?
- Thread starter Geo
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Hello everyone. I registered on this forum just to reply to this topic. I thought I might share some insight into this topic, since I'm in the microelectronics/nanotechnology field.
The most obvious and simplest answer to the question is "yield". While the 65nm process may have started, any transition to a smaller gate size will result in horrible initial yields. Previous generations (like 2-3 years ago) ironed out these problems relatively quickly, but current technologies are a bit trickier (ie. around 90nm) to work with.
The only fab company that can reliably push out 65nm chips at the current moment is Intel. Nearly all other fabs concentrate their production power at the 90nm node.
Note that the 65nm process has its own set of problems; some boards were remarking on the fact that AMD's 65nm X2 chips actually had slower cache than their 90nm counterparts. Whether that is due to the 65nm gate size or a design flaw is up for discussion. Moreover, 65nm does not magically imply lower power consumption because of a lower turn-on voltage; leakage currents and other various effects tend to be more prominent as sizes get smaller.
The most obvious and simplest answer to the question is "yield". While the 65nm process may have started, any transition to a smaller gate size will result in horrible initial yields. Previous generations (like 2-3 years ago) ironed out these problems relatively quickly, but current technologies are a bit trickier (ie. around 90nm) to work with.
The only fab company that can reliably push out 65nm chips at the current moment is Intel. Nearly all other fabs concentrate their production power at the 90nm node.
Note that the 65nm process has its own set of problems; some boards were remarking on the fact that AMD's 65nm X2 chips actually had slower cache than their 90nm counterparts. Whether that is due to the 65nm gate size or a design flaw is up for discussion. Moreover, 65nm does not magically imply lower power consumption because of a lower turn-on voltage; leakage currents and other various effects tend to be more prominent as sizes get smaller.
With the higher leakage, how likely would it be that heat dissipation would actually get worse assuming they manage to reduce the size of the die considerably? (i.e. higher thermal density) One would expect them to handle the leakage appropriately and Dave Baumann has said that it isn't particularly bad at 65nm.
Perhaps they should add heat spreaders to the dice ala Intel/AMD and design the heatsinks to be socketed onto the heat spreader to get that extra bit of contact on the side edges...
Perhaps they should add heat spreaders to the dice ala Intel/AMD and design the heatsinks to be socketed onto the heat spreader to get that extra bit of contact on the side edges...
The leakage would be for a similar size of ASIC - given that a 65nm part would be a shrink of the currently existing ASIC it will be considerably lower TDP / heat output.
Well, as I noted upstream, "yield" answers have to take into account that RV610 (in particular) and RV630 are already at 65nm, and they would also be highly sensitive to yield considerations. Possibly not *quite* as sensitive as Xenos, but in the same neighborhood, and for Xenos you'd have the heat savings considerations and related items associated from that (less power, smaller power brick, smaller heatsinks, less weight, etc) to take into consideration (where you wouldn't as much for the gpus where they're trying to keep that more in a range and trade for increased performance instead).
So I'm not buying "yield" as an answer. . .at least not by itself.
So I'm not buying "yield" as an answer. . .at least not by itself.
Hmm... perhaps we the consumers have yet to see them because MS wanted a healthy supply of 360 units and the production scale for the 65nm just isn't that high yet? (like, they may have good yields, but if everything is being put to 90nm production at the factory...)
(Hmm I think a previous reply of mine might have disappeared...)
There was a seminar here about a year ago from a Micron engineer about their imaging chips. One graduate student asked about their yields, and the presenter quickly replied, "No company would ever comment publically about their yields."
I thought that comment was quite apt.
Anyways, as to the yield theories being tossed around, one has to wonder how the RV610/630 are doing in the channel. Are they in high or short supply? How does it compare to the needs of 360 manufacturing?
Admittedly, I don't know much about TSMC's 65nm technologies and what techniques they employ. However, I do have a healthy sense of skepticism as to how far their 65nm technology has gone. (In fact, I wasn't even aware that TSMC actually had well-developed 65nm capabilities)
I should probably rephrase a previous statement of mine: I did not mean to say that TDP/heat output would be greater at 65nm, but rather that these are issues, along with other molecular-sized issues, that must be sorted out at this regime. Any defect in the dielectric would basically mean that the transistor is gone.
Yeah. Shouldn't happen again for you. We have a fairly aggressive anti-Spam filter for noobies first few posts. I approved that post but it was a dup, so I deleted it.
Well, *right at the moment* I'd say with confidence that RV610 and RV630 are both handily out-selling XB360 (I'm including OEM + channel), and by significant percentages. However, I wouldn't rule out capacity at 65nm as a possible issue. Possibly they were looking at what they'd need on hand for the Holiday season and didn't feel confident enuf yet to ramp/stockpile to that volume in competition with TSMC's other high volume 65nm customers.
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