So why isn't Xenos 65nm yet?

[Geo]

This is starting to bother me. In a world where Xenos was first to 90nm (okay, so R520's problems had a bit to do with that, but still) in the summer of 2005 (when they began shipping them to MS in volume), here we are two years later and it's *still* 90nm. Why? The quite sizable advantages to a shrink to 65nm seem too evident to even bear much discussion. Is "yields at the 65nm node" the answer? I can't see it, personally. . . or you'd have to make an argument for why "yields" are less important for the already-shipping 65nm RV6 line than it would be for Xenos. This strikes me as a pretty difficult case to make.

So I keep coming back to the interface with the edram daughter die as being the likely sand in the gears on a shrink. Is it possible to marry a 65nm Xenos die with a 90nm edram die? Would it require significant re-engineering/verification of the interface between them such that you might rather wait for 65nm edram instead? The fact that TSMC is now reported to be doing the daughter die now at 90nm have anything to do with the delay in getting Xenos moved to 65nm?

 

[AlNom]

So I keep coming back to the interface with the edram daughter die as being the likely sand in the gears on a shrink. Is it possible to marry a 65nm Xenos die with a 90nm edram die? Would it require significant re-engineering/verification of the interface between them such that you might rather wait for 65nm edram instead? The fact that TSMC is now reported to be doing the daughter die now at 90nm have anything to do with the delay in getting Xenos moved to 65nm?

I do find it strange that TSMC is implementing the daughter die at 90nm when they have 65nm production capability for not only regular advanced chip designs but also for eDRAM. They announced that capability back in March. Perhaps the nature of the daughter die is irregular enough with the processing elements that it makes it even trickier to fabricate.

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=197006869
February 2007

However, Niebel says IBM's eDRAM is little different than putting 1 Gbyte of DRAM next to a central processor. "It's a lengthy process because you are writing the memory into the same chip. Traditionally, chipmakers can make the memory better and the logic suffers or the logic improves and the memory suffers. ...

That's "IBM's eDRAM", but it sounds like it would be a general hardware design issue, and perhaps TSMC isn't ready for that level of integration at 65nm.

As for why they don't mix the two processes... It shouldn't really be an issue considering how often it's done elsewhere. It might be that MS has a ridunkulous supply of 90nm parent dice. :|

 

[tuna]

Isn't RSX still on a 90nm as well? It seems really difficult to move GPU's to smaller processes, but I don't know why. Have this been discussed before?

 

[Acert93]

Last I heard was 65nm was slated for this fall.

It is concerning because a process node shrink, you would think, is a priortiy for cost reduction reasons. The only reason I have received from a reliable source (and he is very reliable, but I find it a weak suggestion) is that he was told Microsoft did shift a lot of their engineering department's efforts over to the RROD issue to engineer a solution for all the bricked units. I don't know how big MS's engineering department is, and would assume ATI was contracted for process shrinks, but this source indicated the RROD ate up a lot of people. I don't really see how that is possible, but that is what I heard.

I know 65nm is holding Laa-yosh up... and probably me too.

 

[Gerry]

The only reason I have received from a reliable source (and he is very reliable, but I find it a weak suggestion) is that he was told Microsoft did shift a lot of their engineering department's efforts over to the RROD issue to engineer a solution for all the bricked units.

Wasn't that Dean Takahashi theory? Can't quite remember now...

 

[Acert93]

Isn't RSX still on a 90nm as well? It seems really difficult to move GPU's to smaller processes, but I don't know why. Have this been discussed before?

It can be difficult, but ATI already has 65nm chips in production. Considering Xenos was designed with a power/heat envelope to work in a confined space (hence the frequency difference with R520; R520 was 625MHz I think). Going to 65nm should require less power and produce less heat.

 

[Geo]

Going to 65nm should require less power and produce less heat.

There are all kinds of indirect goods from that quite aside from the direct savings on Xenos itself. And RROD is suspected to be a long-term heat issue, isn't it? Like I said, nearly "Duh!" level of obviousness for being a high priority.

If one takes Takahashi's book as a source, they could be a year behind on getting Xenos shifted to 65nm. He seemed to be expecting it for Fall 2007. Given when RV6 showed up, probably TSMC gets at least some significant portion of that delay, but I'm still at a loss to explain why Xenos would be many months behind RV6 for priority in getting to 65nm. . .

 

[AlNom]

Are the RRODs still occurring with the new units that feature the extra heatsink attachment? They can't have seriously pulled that many engineers just to come up with that idea...

With respect to the parent/daughter dice, another thing to consider is the motherboard. I don't know how flexible the design was for integrating the CPU or GPU, but it would require differences in the capacitors and resistors that normally lie directly underneath those chips. You can compare Intel's 90nm and 65nm Pentium 4's in that regard. Furthermore, a new chipset was required to even use the 65nm Intel CPUs despite having the same socket/pin count. Even the Elite motherboard saw a numerous amount of component changes, presumably more efficient or higher quality components.

Given the fixed nature of the console design, it might not have been worth it to have that extra design for a 65nm parent die and a 90nm daughter die when they can wait a few more months.

 

[Asher]

My barely 2 month old refurbished 360 had the new HSF and still RRoD'ed me. They think it's my power adapter, though.

 

[lentoPastel]

Last I heard was 65nm was slated for this fall.
It is concerning because a process node shrink, you would think, is a priortiy for cost reduction reasons. The only reason I have received from a reliable source (and he is very reliable, but I find it a weak suggestion) is that he was told Microsoft did shift a lot of their engineering department's efforts over to the RROD issue to engineer a solution for all the bricked units. I don't know how big MS's engineering department is, and would assume ATI was contracted for process shrinks, but this source indicated the RROD ate up a lot of people. I don't really see how that is possible, but that is what I heard.
.

maybe the RROD affected changing the process to 65nm in more ways than leveraging resources to solve the problem of bricked consoles... maybe they didnt really know the cause of the RROD, so the shrink process was delayed until determining the real cause and fix it (assuming the problem is not heat alone). It would be very embarrasing to go 65nm and still having RRODs...

 

[Rangers]

Because every die shrink these days is like pulling teeth and takes longer and longer every time, basically.

 

[Geo]

Because every die shrink these days is like pulling teeth and takes longer and longer every time, basically.

You really want to argue it takes more work and time to shrink Xenos than produce RV610 and RV630 at 65nm starting from 80nm R600 as a base?

Maybe ATI's teams didn't have the time, or convinced MS they would benefit from the experience of letting ATI's parts go first at 65nm.

 

[Acert93]

Maybe ATI's teams didn't have the time, or convinced MS they would benefit from the experience of letting ATI's parts go first at 65nm.

Considering the sort of cash they could save migrating to 65nm this fall, with millions of units being sold, it would take some heavy convincing. It isn't just costing them money, but also marketshare due to implicated price reductions.

You would think this would be a huge priority.

 

[Geo]

'tis a puzzlement. Someone should start a thread on it. Oh, wait. . .

 

[Dave Baumann]

Maybe ATI's teams didn't have the time, or convinced MS they would benefit from the experience of letting ATI's parts go first at 65nm.

Thats a bit of a stretch.

 

[Dave Baumann]

I do find it strange that TSMC is implementing the daughter die at 90nm when they have 65nm production capability for not only regular advanced chip designs but also for eDRAM.

You would also want to consider the wafer pricing for the EDRAM processes.

 

[Geo]

Thats a bit of a stretch.

It is, but at the moment any theory on the subject feels like a stretch. Yet there must be a real reason somewhere. . .

 

[Geo]

You would also want to consider the wafer pricing for the EDRAM processes.

Care to weigh in on how trivial/non-trivial it is to mix-and-match processes for parent and daughter?

 

[Shifty Geezer]

Could the same reason be the reasons for limited die shrinks across all the consoles? They're all behind schedule on process shrinks it seems. The latest we've heard about IBM's Cell shrink to 65nm was very limited gains, and in the case of PSP Sony even decided 65nm wasn't worth it. The only explanation I can think of is a reliance on technologies that aren't shrinking so well at the moment, but I don't know the tech details of Xenos versus ATi's other 65nm parts. Does the eDRAM process share techniques in the CPU processes for both consoles?

 

[AlNom]

eDRAM production is pretty different from what I understand. NEC has a page of info (I'm just reading now) that may give some clues as to the difficulty in integrating eDRAM with regular logic.

I'm not sure if NEC is that much farther ahead with the technology than TSMC or if TSMC actually has a different solution for going to smaller processes though. :|

http://www.am.necel.com/process/edramstructure.html