Tile accelerated display list rendering.
Minimizing unnecessary data calculation and transfer is the point of efficient design. The difference between PowerVR and other approaches is that PowerVR starts from the assumption that it can be completely efficient while other designs assume that they won't be and just do their best from there.
PowerVR attempts to collect the whole scene into display lists for evaluation of just the visible geometry while employing a robust tile accelerator to divide it into a large number of internally manageable, small tiles of screen. The use of display lists gives knowledge of the scene's composition to the processor and therefore the ability to determine just the visible parts, resulting in a pixel fillrate that's unconditionally effective. The use of small tiles saves chip space by not requiring a high amount of costly embedded memory while still keeping processing on-chip and independent from the frame buffer to enable unconditionally precise internal color blending, depth sorting, volume/stencil buffering, MRTs, etc. In order to simultaneously accomplish these separate vertex and pixel goals, the processing units must be structured to be highly parallel and independent so that they can work quickly on separate frames and not get stalled by waiting for each other (similar in effect to unified pipelines). PowerVR processors as a whole then become modular and therefore very scalable and also very fast in fillrate for operations which work from this parallel structure, like visible surface determination (HSR) for opaque overdraw and like volumes/stencils for stencil performance.
Between the advantages of rendering with on-chip bandwidth and of knowing the scene's composition, anti-aliasing, via both supersampling or multisampling, can be sampled directly from the tiles to the render buffer without extra external space or bandwidth requirements. Indeed, MBX boasts FSAA4FREE (4xAA).
Now, the N-Gage2 images might actually have promosampled FSAA, but an FSAA advantage for tile accelerated display list renderers is very real.
With mobile phone sales in the hundreds of millions of units each year, the amount of production and marketing that could be necessary to capture share in the PC space has been viewed as too risky for its market size by semiconductor companies not already established there. The established companies have expressed reservation with regards to tile accelerated display list rendering over issues of compatibility and its ability to deal with extreme rendering scenarios, but the approach is different in no fundamental ways and can render in immediate mode, while still retaining a degree of advantage in efficiency, if scene conditions became too extreme and the ideal deferment was impractical.