As has been indicated, each SGX variant is the result of customized performance and sometimes features, not just the scaling of ALUs and TMUs. In the context of 200 MHz and < 50% shader load:
IMG was originally very specific about the performance of the 530, indicating a figure down to the half-million, 13.5M tri/sec, which logically implies that they weren't being too rough about their rounding. They later charted the 520 at 7M tri/sec, the 530 at 14M tri/sec, and the 540 at 28M tri/sec. Some of the pixel fill numbers from the old SGX tech docs did imply, as was mentioned, that the 520 was somehow even less than half of the 530 (the cancelled 510 was even far less, using a USSE-lite pipeline.)
All indications were that the 53x family shared similar geometry performance characteristics. Indeed, GMA 500 docs state a performance of 1 triangle per 15 cycles which equals 13.3M tri/sec, and Intel even rates it explicitely at 13M tri/sec where they commonly set the clock at 200 MHz. NEC claimed 15M tri/sec for the 535 in their NaviEngine SoC, so the 13M tri/sec range seems very probable for the 53x line of variants.
I've been inclined to believe IMG has customized each successive variant for incrementally higher geometry performance as provided in their original, respective press releases: 35M tri/sec for the 543, ~40M tri/sec for the 545, 100M tri/sec for the cancelled 555, and 95% of 35M tri/sec multiplied by the number of MP cores.
