RSX patent?

[j^aws]

GPU rendering to system memory

Abstract
A graphics processing subsystem uses system memory as its graphics memory for rendering and scanout of images. To prevent deadlock of the data bus, the graphics processing subsystem may use an alternate virtual channel of the data bus to access additional data from system memory needed to complete a write operation of a first data. In communicating with the system memory, a data packet including extended byte enable information allows the graphics processing subsystem to write large quantities of data with arbitrary byte masking to system memory. To leverage the high degree of two-dimensional locality of rendered image data, the graphics processing subsystem arranges image data in a tiled format in system memory. A tile translation unit converts image data virtual addresses to corresponding system memory addresses. The graphics processing subsystem reads image data from system memory and converts it into a display signal.
...

GPU rendering to system memory

I haven't had time to read it but the patent refers to GPU rendering to system memory ala PS3/RSX...

 

[blakjedi]

Dont all consoles do this??????

 

[Carl B]

Without even reading the patent, could it be associated with Turbo-Cache rather than RSX specifically?

 

[Shifty Geezer]

No. PS2 renders to eDRAM, as does GC. XB renders to system RAM. The point here is the PC doesn't do this, so an nVidia patent about rendering to RAM is more likely for a console part where we know this is happening. Thought strangely the PS3 hasn't realy got what one would call a system memory structure. The two pools of RAM are approximately divided into system RAM and video RAM even though the two are addressable by CPU and GPU. The patent could therefore being to cover render to system memory, perhaps as a precursor to GPGPU functionality outputting to system RAM for access by the CPU?

 

[version]

4*4 tiles= 16 simd

 

[London Geezer]

4*4 tiles= 16 simd

.. and he sprints off... Another hit and run!

 

[Qroach]

No. PS3 renders to eDRAM

what say who now?? PS3 has edram on the GPU? I must have missed that.

 

[version]

i think rsx rendering to tiles, and no edram but a big tilecache

 

[London Geezer]

what say who now?? PS3 has edram on the GPU? I must have missed that.

He meant PS2 (i guess, cause then he mentions GC and Xbox....)

 

[Shifty Geezer]

what say who now?? PS3 has edram on the GPU? I must have missed that.

Sorry, typo. PS2 renders to eDRAM. I'll edit that.

 

[Powderkeg]

No. PS2 renders to eDRAM, as does GC. XB renders to system RAM. The point here is the PC doesn't do this, so an nVidia patent about rendering to RAM is more likely for a console part where we know this is happening.

Yes, PC's DO do this. It's called Turbocache, and any Nvidia GPU that uses Turbocaching does this. It's part of the G70 GPU design, and not limited to RSX. (Although it is modified for RSX)

 

[Qroach]

Sorry, typo. PS2 renders to eDRAM. I'll edit that.

ahh, ok no worries

 

[Shifty Geezer]

Yes, PC's DO do this. It's called Turbocache, and any Nvidia GPU that uses Turbocaching does this. It's part of the G70 GPU design, and not limited to RSX. (Although it is modified for RSX)

Well, okay then. Prior to G70 (which only released a few months ago) PC didn't do this. And in what way is this feature actually used on G70? Just because the feature is there doesn't mean anyone actually renders to system RAM, and if they DO render to system RAM, why? They've got shedloads of fast VRAM to use!

 

[Carl B]

Well, actually the 6800 generation had it as well. The NV44 chip is a Turbo-Cache chip.

 

[Shifty Geezer]

But is it used?

 

[Titanio]

To clarify - Turbocache lets you render to system memory? I thought it was really just for pulling things over from system memory, but I'm not very au fait with it.

 

[Carl B]

Oh it's used alright!

(It sucks, but it's used )

Some cards using the chip

Turbo-Cache Review

 

[Dave Baumann]

AGP has always allowed for AGP texturing, which allows textures to be addressed directly from system RAM - that was a requirement of AGP, and the ability to swap textures between graphics and system RAM was also a requirement.

Because this was limited to texturing NVIDIA's graphics had previously only been able to render (send colour / Z data) to their graphics RAM, meaning that framebuffer sizes an depths supported were limited by the memory (but thats not really been much of a limitation). On NV44 (6200) NVIDIA introduced the capability of rendering to system RAM so that the framebuffer can now be distributed between local and system RAM - the reason for doing it them was that PCI Express was available and the bandwidths made it more feasible.

NVIDIA call this "TurboCache" and ATI have "HyperMemory" doing the same thing; the difference is that ATI could actually render to system memory on all their parts since R300 (Radeon 9700) but didn't due to performance implications on AGP - the "HyperMemory" brand was just brought out because its now become feasible to do it with PCI Express.

 

[j^aws]

Some queries, do current TurboCache GPU's use micro-tiling? With these TurboCache GPU's local VRAM, can the CPU address that VRAM?

...[0056] FIGS. 5A and 5B illustrate a system of organizing display information in system memory to improve rendering performance according to an embodiment of the invention. To leverage the two-dimensional locality of image data generated by the graphics processing subsystem, an embodiment of the invention organizes image data as a set of tiles. Each tile includes image data for a two-dimensional array of pixels. FIG. 5A illustrates a portion of an image 500. Image 500 is divided into a number of tiles, including tiles 505, 510, and 515. In the embodiment of FIG. 5A, each tile includes a 4 by 4 array of pixels. However, square and non-square tiles having any number of pixels may be used in alternate embodiments. In FIGS. 5A, each pixel is labeled with the pixel's row and column in the image 500. For example, tile 505 includes the first four pixels in each of the first four rows of the image 500.
...

The above tiling is interesting as the size is small enough to fit into SPE's local store!

 

[Shifty Geezer]

There was another patent regarding tiles and small caches or something to store them, with an addressing mechanism. I wouldn't be surprised if they were designed to fit with the SPE's. We've been told Cell and RSX are cache coherant (right term?) and can share data directly. Must be a reason for this!