Just thought this was pretty interesting when Shogmaster brought it up.
Anyway, do you guys think a dual core 750VX (G3+Altivec) with 1MB of L2 cache each running at 1.6GHz would make for a powerful Revolution CPU? How would it compare to a dual core 970FX? Anyway I found this bit of info on the 750GX.
According to Mark Schaffer, an Advanced Technology Engineer with IBM:
Manufactured in IBM’s advanced 0.13-micron copper process with Silicon-on-Insulator technology, the 750GX will be offered at frequencies up to 1.1 GHz. The 750GX expands the capabilities of the IBM PowerPC 7xx processor family to support more performance-demanding and power-sensitive applications. The new processor is ideally suited for a variety of systems, including networking, communications, storage, imaging, computing and consumer applications.
The 750GX is architecturally based on the PowerPC 750FX processor, and implements several enhancements that address the performance requirements of embedded applications (see Figure 1). The 750GX includes 1 MB of internal L2 cache, 4-way set-associative, running at core frequency with cache locking by way, additional L1 and L2 cache buffers allowing pipelining of up to four data cache miss operations, and the capability for up to 200-MHz operation of the 60x system bus interface with additional bus pipelining.
The integrated 1 MB of L2 cache operates at the processor’s core frequency, providing minimal latency for instruction fetch operations and data load operations that hit in the L2 cache. The larger size of the internal L2, twice that available on the 750FX, provides more on-chip memory storage for performance-critical application code and data, and may provide a significant performance improvement, due to the size alone. In addition, the L1 data cache path to the Bus Interface Unit (BIU) and the L2 cache reload path to the L1 data cache are 256 bits wide. With these wide data paths, cache line data bursts can be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. With 1 MB of low-latency integrated L2 cache, the 750GX is designed to reduce the overall system cost and power by eliminating the need for external L3 memory arrays and lowering the board space requirements.
The 1-MB L2 cache is four-way set-associative, and supports cache locking by way. Any combination of L2 cache ways can be locked, and the locked area becomes a direct-mapped memory space managed by software. Critical code and data tables can be managed directly with software, and will not be pushed out or replaced in a locked cache. This can be beneficial for applications that require deterministic behavior or for key interrupt service routines.
Cache line miss buffers have been added between the L1 data cache and the L2 cache as well as between the L2 cache and the BIU, allowing for up to four-deep pipelining of L1 cache miss transactions. The four transactions can be either four data cache miss transactions or a combination of three data cache miss transactions and one instruction cache miss transaction. In addition, the BIU in the 750GX has been enhanced to provide support for the deeper cache miss pipelining and can now pipeline up to five load/store bus transactions, four from the L2 cache miss queues and one from the L2 cache cast-out buffer. With this enhanced pipelining from the L1 cache through the L2 cache and out to the bus interface unit, the 750GX is designed to improve the overall system performance and bus utilization, allowing applications to take advantage of the higher processing capability that the 750GX processor offers.
The L2 cache has also been enhanced to provide an instruction-side-only mode, which allows only the L1 instruction cache transactions to be allocated within the L2 cache. Data-side transactions are not allocated in the L2 and are read from and written to memory directly from the L1 data cache. This mode is useful for applications that do not benefit from the data-side cache and improves the performance of the L2 cache for the instruction side by not replacing L2 cache lines due to data load and store operations.
The 750GX is fully user-code-compatible with the other members of the IBM 7xx processor family, providing an easy software-migration path to higher processing performance. In addition, the 750GX is pin- and voltage-compatible with the 750FX, eliminating the need for a board redesign to achieve higher performance and allowing for the use of a common board design across a variety of applications with different performance requirements
The package and chip design are both optimized for the high speeds of the processor core and bus. The 21x21-mm 292-ball Ceramic Ball Grid Array (CBGA) package has a partially depopulated pin-out for ease of board layout with the 1.0-mm pitch of the balls, allowing decoupling capacitors to be placed on the underside of the board, in a tightly grouped pattern within the outline of the processor. The pin-out incorporates the full 60x bus interface, including parity signals, but still fits into a small footprint on a board by eliminating the backside L2 interface and using the small pitch.
750VX: 1.5 GHz to 2GHz, Altivec, 1 MB L2 cache 12.5W @ 1.6 GHz?
750CXe/750FX/750GX
Frequency: 400 - 600 MHz/600 - 900 MHz/733 MHz - 1.1 GHz
Process: 0.18 micron/0.13 micron/0.13 micron
Die size: 42.7 mm²/36.6 mm²/51.9 mm²
L2 cache: 256 KB 2-way SA/512 KB 2-way SA/1 MB 4-way SA
Cache miss pipelining: 1 instr, 1 data/1 instr, 1 data or 2 data/1 instr, 3 data or 4 data
Typical power: 6.0 W @ 600 MHz/5.4 W @ 800 MHz/8.0 W @ 1 GHz
Bus speed: 133 MHz/Up to 200 MHz/Up to 200 MHz
Core voltage: 1.8 V nominal/1.45 V nominal/1.45 V nominal
Anyway, do you guys think a dual core 750VX (G3+Altivec) with 1MB of L2 cache each running at 1.6GHz would make for a powerful Revolution CPU? How would it compare to a dual core 970FX? Anyway I found this bit of info on the 750GX.
According to Mark Schaffer, an Advanced Technology Engineer with IBM:
Manufactured in IBM’s advanced 0.13-micron copper process with Silicon-on-Insulator technology, the 750GX will be offered at frequencies up to 1.1 GHz. The 750GX expands the capabilities of the IBM PowerPC 7xx processor family to support more performance-demanding and power-sensitive applications. The new processor is ideally suited for a variety of systems, including networking, communications, storage, imaging, computing and consumer applications.
The 750GX is architecturally based on the PowerPC 750FX processor, and implements several enhancements that address the performance requirements of embedded applications (see Figure 1). The 750GX includes 1 MB of internal L2 cache, 4-way set-associative, running at core frequency with cache locking by way, additional L1 and L2 cache buffers allowing pipelining of up to four data cache miss operations, and the capability for up to 200-MHz operation of the 60x system bus interface with additional bus pipelining.
The integrated 1 MB of L2 cache operates at the processor’s core frequency, providing minimal latency for instruction fetch operations and data load operations that hit in the L2 cache. The larger size of the internal L2, twice that available on the 750FX, provides more on-chip memory storage for performance-critical application code and data, and may provide a significant performance improvement, due to the size alone. In addition, the L1 data cache path to the Bus Interface Unit (BIU) and the L2 cache reload path to the L1 data cache are 256 bits wide. With these wide data paths, cache line data bursts can be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. With 1 MB of low-latency integrated L2 cache, the 750GX is designed to reduce the overall system cost and power by eliminating the need for external L3 memory arrays and lowering the board space requirements.
The 1-MB L2 cache is four-way set-associative, and supports cache locking by way. Any combination of L2 cache ways can be locked, and the locked area becomes a direct-mapped memory space managed by software. Critical code and data tables can be managed directly with software, and will not be pushed out or replaced in a locked cache. This can be beneficial for applications that require deterministic behavior or for key interrupt service routines.
Cache line miss buffers have been added between the L1 data cache and the L2 cache as well as between the L2 cache and the BIU, allowing for up to four-deep pipelining of L1 cache miss transactions. The four transactions can be either four data cache miss transactions or a combination of three data cache miss transactions and one instruction cache miss transaction. In addition, the BIU in the 750GX has been enhanced to provide support for the deeper cache miss pipelining and can now pipeline up to five load/store bus transactions, four from the L2 cache miss queues and one from the L2 cache cast-out buffer. With this enhanced pipelining from the L1 cache through the L2 cache and out to the bus interface unit, the 750GX is designed to improve the overall system performance and bus utilization, allowing applications to take advantage of the higher processing capability that the 750GX processor offers.
The L2 cache has also been enhanced to provide an instruction-side-only mode, which allows only the L1 instruction cache transactions to be allocated within the L2 cache. Data-side transactions are not allocated in the L2 and are read from and written to memory directly from the L1 data cache. This mode is useful for applications that do not benefit from the data-side cache and improves the performance of the L2 cache for the instruction side by not replacing L2 cache lines due to data load and store operations.
The 750GX is fully user-code-compatible with the other members of the IBM 7xx processor family, providing an easy software-migration path to higher processing performance. In addition, the 750GX is pin- and voltage-compatible with the 750FX, eliminating the need for a board redesign to achieve higher performance and allowing for the use of a common board design across a variety of applications with different performance requirements
The package and chip design are both optimized for the high speeds of the processor core and bus. The 21x21-mm 292-ball Ceramic Ball Grid Array (CBGA) package has a partially depopulated pin-out for ease of board layout with the 1.0-mm pitch of the balls, allowing decoupling capacitors to be placed on the underside of the board, in a tightly grouped pattern within the outline of the processor. The pin-out incorporates the full 60x bus interface, including parity signals, but still fits into a small footprint on a board by eliminating the backside L2 interface and using the small pitch.
750VX: 1.5 GHz to 2GHz, Altivec, 1 MB L2 cache 12.5W @ 1.6 GHz?
750CXe/750FX/750GX
Frequency: 400 - 600 MHz/600 - 900 MHz/733 MHz - 1.1 GHz
Process: 0.18 micron/0.13 micron/0.13 micron
Die size: 42.7 mm²/36.6 mm²/51.9 mm²
L2 cache: 256 KB 2-way SA/512 KB 2-way SA/1 MB 4-way SA
Cache miss pipelining: 1 instr, 1 data/1 instr, 1 data or 2 data/1 instr, 3 data or 4 data
Typical power: 6.0 W @ 600 MHz/5.4 W @ 800 MHz/8.0 W @ 1 GHz
Bus speed: 133 MHz/Up to 200 MHz/Up to 200 MHz
Core voltage: 1.8 V nominal/1.45 V nominal/1.45 V nominal
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mrgreen: ), but from what I've read, on a technical level, gekko doesn't have a typical SIMD implementation, but rather a "split" FPU. I suppose in practice it makes little difference though...