Quick Question on PS3 CPU

london-boy said:
Tim said:
It is there, it might be broken. Having redundancy increases yields, if there is an error in a the chip the SPE where the error can be disabled and the chip sold as a 1+7 chip instead of being thrown away - this reduces overall cost.

Redundancy is nothing new there has always been redundant cache lines, the new is that cores in multi core design is used for redundancy.
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But they still have almost and entire year to get this chip right. That's a lot of time in processors terms...
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If they ship in spring 2006 and if by change they are making simultaneous launch they probably have to start manufacturing much sooner than that. I don't know maybe they'l have like six months?.

edit: and PS3 seems to be quite expensive to manufacture as it is, and even with 7 spe's it seems to have 2x processor power over X360 so I think that reducing cost disapling 1 spe is a smart move.
 
Dr Evil said:
If they ship in spring 2006 and if by change they are making simultaneous launch they probably have to start manufacturing much sooner than that. I don't know maybe they'l have like six months?.
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6 months is still a lot.
But honestly, i'd rather have a fully working 7SPEs cell than a mostly working 8SPEs one.
 
london-boy said:
Dr Evil said:
If they ship in spring 2006 and if by change they are making simultaneous launch they probably have to start manufacturing much sooner than that. I don't know maybe they'l have like six months?.
Click to expand...

6 months is still a lot.
But honestly, i'd rather have a fully working 7SPEs cell than a mostly working 8SPEs one.
Click to expand...

Hmm your too fast( beat my edit),

It doesnt' really matter if it is 7/8 or 7/7 does it, I mean 1 year after you have bought the machine and playing a game I bet that you are not upset about that :)
 
Isn't the PS3 Cell an 8 SPE after all?

The 8th SPE was in the diagrams, but it was marker "reserved for redundancy" or something like that, that would suggest it has something to do with DRM.

So, basically it's the 8 SPU Cell that was known, only one of them has been isolated for special task.
 
rabidrabbit said:
Isn't the PS3 Cell an 8 SPE after all?

The 8th SPE was in the diagrams, but it was marker "reserved for redundancy" or something like that, that would suggest it has something to do with DRM.
Click to expand...

Actually I think the "reserved for redundancy" suggest that it is reserved for redundancy.
 
Reserved for Rednundancy would implied they print 8 SPU's with a 1 SPU failsafe. One knackered SPU still leaves a full compliment of 7 intended. I guess they were hoping for 8 but haven't been getting the yields, but had bucketloads of working 7's so thought 'soddit, we'll go with seven sus then and be on the safe side'
 
Maybe they could orient the chips at the edges of the wafer - where cracks and impurities most often occur - so that the SPEs faces outward. That way the all important PPE won't get damaged as often? Just a tought.
 
Dr Evil said:
edit: and PS3 seems to be quite expensive to manufacture as it is, and even with 7 spe's it seems to have 2x processor power over X360 so I think that reducing cost disapling 1 spe is a smart move.
Click to expand...

Well i just think they could put "something else" in there, instead of having an inactive group of transistors. Don't know... a ... PPU :LOL:

/runs
 
You don't seem to understand what redundancy implies (neither did I).
It means that any of the eight SPEs can be defective and they will still have a useable processor. This is not a new idea as such, only it has only been possible to apply it to memory up until now.
 
Squeak said:
You don't seem to understand what redundancy implies (neither did I).
It means that any of the eight SPEs can be defective and they will still have a useable processor. This is not a new idea as such, only it has only been possible to apply it to memory up until now.
Click to expand...

Oh right! I had the wrong idea then...
 
These FLOPS numbers was single precision, right? (Okay, SP is enough for most of the tasks, indeed in a console.) There were figures here, too, on double precision, but those counted only on the PPE's FPU, I think. (So the number was rather low.) But, AFAIK both the VMX units and the SPE's has also a DP unit in each... Anyone know how much DP FLOPS the Cell can do (at a given GHz)?
 
dess said:
These FLOPS numbers was single precision, right? (Okay, SP is enough for most of the tasks, indeed in a console.) There were figures here, too, on double precision, but those counted only on the PPE's FPU, I think. (So the number was rather low.) But, AFAIK both the VMX units and the SPE's has also a DP unit in each... Anyone know how much DP FLOPS the Cell can do (at a given GHz)?
Click to expand...

http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/D9439D04EA9B080B87256FC00075CC2D

Page 5 said:
Each Synergistic Processor Unit (SPU) is a four-way SIMD unit optimized for single-precision (32-bit) floating point but can support double-precision math at reduced performance (about ten times slower).
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Jawed
 
dess said:
london-boy said:
dess said:
Anyone know how much DP FLOPS the Cell can do (at a given GHz)?
Click to expand...

Why does it matter?
Click to expand...
To have the right numbers? In addition to satisfact my curiosity. :)
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The performance hit for double precission is 10x (acording to IBM). But as someone said it is not really important in a console.
 
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