Question about PS3s disabled SPE

[mrboo]

We all kow about the 8th SPE being disabled for redundancy reasons, but im assuming that it still has its 256k Local store along with it, so my question is :

Could the enabled SPE's use the 256kb of Local store from the disabled SPE?

Or is the Local store limited to its designated SPE?

 

[DeanA]

Could the enabled SPE's use the 256kb of Local store from the disabled SPE?

As it is, the entire SPU is disabled. I don't think it would help anyway, as the redundancy aspect also covers faults in the local store area. It would make no sense for some consoles to have the additional 256kb (where the LS area was working, but the fault was elsewhere), and other consoles to have nothing.

Dean

 

[mrboo]

Ah, thanks for the reposnse

 

[blakjedi]

Question: Does disabled mean someone physically broke the connection on the EIB to that SPE? Or is is a firmware/ROM disabling of a potentially good SPE? Is it the same SPE in every Cell chip?

 

[Ragnarok]

Question: Does disabled mean someone physically broke the connection on the EIB to that SPE? Or is is a firmware/ROM disabling of a potentially good SPE? Is it the same SPE in every Cell chip?

Nope, it's whatever SPE didn't survive the fab process. If they all survived then a default one is chosen to keep all the CPU's on even ground.

 

[3dilettante]

Question: Does disabled mean someone physically broke the connection on the EIB to that SPE? Or is is a firmware/ROM disabling of a potentially good SPE? Is it the same SPE in every Cell chip?

It probably wouldn't be safe to physically destroy the connection between the disabled SPE and the ring bus.

There are a couple options for disabling an SPE. The least intrusive is some kind of firmware setting, but that can be reflashed.

The next is some kind of bridge connection on the substrate (AMD Athlons could have their multipliers changed by reconnecting the small breaks).

The most permanent is using a laser to blow small micro-fuses on the chip itself, which is pretty much impossible to circumvent.

 

[Rufus]

3dilettante: A cheap version of the on-die fuse is simply one that burns from sending too much current through it, instead of having to laser the die. That's how a lot of write-once FPGAs work.

 

[ZoinKs!]

If they all survived then a default one is chosen to keep all the CPU's on even ground.

In my non-expert opinion, it seems likely that a Cell with all 8 SPE's fully functional would be set aside for other purposes. It'd make more sense to put the Golden Sample into a $5,000-6,000 workstation which is sold for a profit rather then in a $500-600 console which is sold for a loss.

 

[xatnys]

I don't know what is meant by this "redundancy" (in this context anyway). Since we're on the subject would someone mind enlightening me? Thanks

 

[Gholbine]

I have a question about the disabled SPE. Given that developers don't know which SPE is disabled, since it will differ from console to console, how are the SPEs numbered? Will the system automatically number them 0 to 6, skipping the disabled SPE?

Also, considering developers can't really control which physical SPE their code runs on (if the hardware numbers them, avoiding the disabled one), how will this affect predictable performance? Is there any memory latency issues for SPEs given their position on the EIB?

 

[Platon]

Another thing, cn one SPE use one others LS? What I man by that if you have one damaged SPE but the LS is OK, while on another SPE that is OK by the LS is damaged can then use the good SPE with the good LS or will the chip have to be scraped, atleast as an PS3 chip...

 

[mrboo]

I have a question about the disabled SPE. Given that developers don't know which SPE is disabled, since it will differ from console to console, how are the SPEs numbered? Will the system automatically number them 0 to 6, skipping the disabled SPE?

Also, considering developers can't really control which physical SPE their code runs on (if the hardware numbers them, avoiding the disabled one), how will this affect predictable performance? Is there any memory latency issues for SPEs given their position on the EIB?

I think they can

 

[DeanA]

Another thing, cn one SPE use one others LS? What I man by that if you have one damaged SPE but the LS is OK, while on another SPE that is OK by the LS is damaged can then use the good SPE with the good LS or will the chip have to be scraped, atleast as an PS3 chip...

LS is an integral part of an SPU core. It's subject to the same redudancy reasoning as the actual instruction side of things. What you describe is a CELL with two broken SPUs.. As such it wouldn't find it's way into a PS3.

Dean

 

[Crossbar]

Also, considering developers can't really control which physical SPE their code runs on

I think they can

Yes, I would be believe that as well, because that is crucial if you want get most out of the Cell.

For example, if you want to reach optimal utilisation of the internal ring bus you'd want to have SPUs frequently communicating with each other placed next to each other, because that allows other parts of the ring bus to be active at the same time.

 

[Platon]

LS is an integral part of an SPU core. It's subject to the same redudancy reasoning as the actual instruction side of things. What you describe is a CELL with two broken SPUs.. As such it wouldn't find it's way into a PS3.

Dean

OK, got it, cheers...

 

[Gholbine]

I think they can

Conceptually yes, but as I said, one of those SPEs is going to be disabled and developers do not control or know which one it is, so they can't always know exactly which physical SPE their code is running on in the real world.

 

[Crossbar]

Conceptually yes, but as I said, one of those SPEs is going to be disabled and developers do not control or know which one it is, so they can't always know exactly which physical SPE their code is running on in the real world.

Kind of irrelevant from the developers point of view in the same sense as we don´t know which ALU an add op is running on a super scalar CPU.

As long as the working SPUs have a correct sequential number following their position on the ring bus, the devs will be just fine.

 

[Gubbi]

Conceptually yes, but as I said, one of those SPEs is going to be disabled and developers do not control or know which one it is, so they can't always know exactly which physical SPE their code is running on in the real world.

But that doesn't matter at all. The developers still see SPU0-6. If the 4th physcal SPU is defective, the developer still experience SPU2 immidiately adjacent to SPU3 from a logical point of view, and more importantly from a ring bus contention point of view

Cheers

 

[Shifty Geezer]

But that doesn't matter at all. The developers still see SPU0-6. If the 4th physcal SPU is defective, the developer still experience SPU2 immidiately adjacent to SPU3 from a logical point of view, and more importantly from a ring bus contention point of view

Cheers

I think gholbine's point is that the physical difference may have an impact on code. The difference from one SPE to another when passing data will be at most one extra 'jump' in distance. Will that add latency or otherwise have a negative impact on code, when the dev writes for SPE0 to send data to SPE1 next door, but the data sent has to travel twice as far because SPE1 is knackered and SPE2 fills the role of SPE1?

 

[Ragnarok]

In my non-expert opinion, it seems likely that a Cell with all 8 SPE's fully functional would be set aside for other purposes. It'd make more sense to put the Golden Sample into a $5,000-6,000 workstation which is sold for a profit rather then in a $500-600 console which is sold for a loss.

I agree, they would most likely set aside fully operational Cells. Unless of course, PS3 yields were slipping too low.