Qualcomm shows working MSM8x60 at CES.

[Arun]

I would've expected at least Broadcom and ST to have some products aimed at 28LP. There's a definite trade-off when going to HP that is unsuitable for handhelds.

I can easily believe that SiON is more cost effective, but I don't agree with "unsuitable". For the same amount of static power with the same target frequency, dynamic power will be *lower*. And keep in mind we're talking 28HPM here, not 28HP. Not only does HPM have lower leakage (and performance) for Standard Vt, it also has a Ultra High Vt option to reach leakage comparable with 28LP. So I really don't see how it's fundamentally unsuitable even if there is a good argument for sticking to SiON a bit longer.

TDP for a 3GHz A15 on 28HP would likely be too high for a lot of current tablet form factors. But like I said, aggressive throttling would help in that regard but the device would almost never be able to sustain that kind of peak frequency.

So dual-core 3GHz A15 is too much, but quad-core 2.5GHz Krait isn't? And indeed you would NOT need to sustain that kind of peak frequency. Even 3GHz+2GHz peak for one third of a second could make a big difference to web browsing.

There's also the problem that the PMIC would have to be severely ramped up to provide that kind of peak current as well. A similar problem existed at 65nm for a 1GHz Scorpion and that was a single-core on a bulk, low-current process. 28HP isn't that big of an improvement power-wise.

I don't know what the Qualcomm PMIC could do that in that timeframe, but there are plenty of PMICs today with multiple 1Amp DC/DCs like the DA9052. Are we really talking more than 900mW for a single core?

Either way, significantly more powerful PMICs already exist, like the WM8326. You could even handle a quad-core A15 with that thing: 2.5A for the 'peak' core, 2.5A for the other 3 cores, 1A for the rest of the system, 1A for I/O. Then you'd need a separate power subsystem for the DDR3, but that's pretty much par for the course anyway.

Just to be clear, we're not talking about 3W TDP for the CPU alone, we're talking about peak power with aggressive thermal throttling resulting in probably a 1W TDP max for the CPU and 1.5W for the full SoC. And that's for a quad-core A15 (NVIDIA Logan?) obviously the majority will be a much more reasonable dual-core.

 

[Ailuros]

metafor/Ailuros: Well, I'd expect T30 to make more money for NV than T20 by Q1 2012, so I'm not sure it matters either way. What you should really compare IMO is the total amount of revenue (ideally gross profit and excluding the baseband part) for dual-core-and-above phones. Of course, that kind of data is even harder to get access to...

NV had high expectations for T2 too; did they claim something like over 50 design wins or was that just some mean gossip that circulated the web? I had my 2nd thoughts back then as I have them today. Yes NV definitely will gain step by step a bigger foothold in the embedded market, but to reach Qualcolmm's smart-phone integration rates it's still a couple of lightyears apart.

 

[Arun]

NV had high expectations for T2 too; did they claim something like over 50 design wins or was that just some mean gossip that circulated the web?

Rayfield said that at MWC 2010, yes. Those were mostly Android 2.2 tablets which got cancelled/revamped when Google decided that they would actively discourage Android 2.2 tablets because they were (rightfully) unhappy with the user experience. So the bad news is they lost most of these design wins. The good news is everyone else lost design wins too, but NVIDIA won the lead platform position for Honeycomb, which gave them many new design wins.

I had my 2nd thoughts back then as I have them today. Yes NV definitely will gain step by step a bigger foothold in the embedded market, but to reach Qualcolmm's smart-phone integration rates it's still a couple of lightyears apart.

Oh, don't get me wrong, Qualcomm is still good ole Qualcomm, master of the known mobile phone universe and beyond. The Atheros acquisition was also a very good one in my book - Qualcomm's WiFi was okay-ish but Atheros is simply the best in the industry and by merging their Bluetooth and GPS teams they can become class-leading there as well. And that's before we even consider the potential synergies with the femtocell business and most importantly the opportunities in other markets that Atheros brings to the table (which Qualcomm claims was the primary reason for the acquisition).

I think if you look at only the tablet and the ultra-high-end smartphone markets, T30/Kal-El will do extremely well. But that's only one part of the overall market. It will be interesting to see if NVIDIA can win in the mid-range over time. Mike Rayfield certainly was adamant that they'd rather focus on the high-end, but the Icera acquisition might change things, as well as the fact Wayne looks like it'll be cheaper than Kal-El. Then again sticking to quad-core A9 (versus dual-core A15 competitors) could cost them in the ultra-high-end if Logan doesn't come fast enough...

 

[ninelven]

as well as the fact Wayne looks like it'll be cheaper than Kal-El. Then again sticking to quad-core A9 (versus dual-core A15 competitors) could cost them in the ultra-high-end if Logan doesn't come fast enough...

...was under the impression Wayne was A15 based... did I miss something?

 

[Arun]

...was under the impression Wayne was A15 based... did I miss something?

It's a much smaller step than either Kal-El or Logan (see: http://assets.vr-zone.net/11197/nvidia.jpg) and Logan is too early for Project Denver. It's not hard to put two and two together... This is basically a tick-tock strategy and Wayne is the tick.

 

[metafor]

I can easily believe that SiON is more cost effective, but I don't agree with "unsuitable". For the same amount of static power with the same target frequency, dynamic power will be *lower*. And keep in mind we're talking 28HPM here, not 28HP. Not only does HPM have lower leakage (and performance) for Standard Vt, it also has a Ultra High Vt option to reach leakage comparable with 28LP. So I really don't see how it's fundamentally unsuitable even if there is a good argument for sticking to SiON a bit longer.

It isn't quite as neat as that. HPM is inherently orders of magnitude more leaky than bulk for the same CMOS configuration, temperature, voltage and process. Yes, if you rework all of your gate structures and size your channels such that the leakage is lower, you can still achieve higher frequencies than with high-frequency bulk-Si designs but you'll never really quite reach the power levels a low-profile LP design will. Simply put, a low-power LP design, while a lot slower, will still provide a sizable (2-4x from the last library models I've seen from TSMC) reduction in static current but at the cost of significantly less frequency headroom.

So dual-core 3GHz A15 is too much, but quad-core 2.5GHz Krait isn't?

All I can say with regards to Krait is ignore all of the numbers -- including target frequency -- you see in slides. Wait for the actual chip.

And indeed you would NOT need to sustain that kind of peak frequency. Even 3GHz+2GHz peak for one third of a second could make a big difference to web browsing.

I don't know how realistic the type of fine-grain control you speak of is. I mean, Atom certainly has a low-enough idle power to fit into a handheld if you very aggressively throttle it, yet I don't think anyone would argue it "fits" into that profile of a device. To me, if a device can't at least handle some type of sustained task at its peak performance, it doesn't belong there. I seem to be the minority in that though....

I don't know what the Qualcomm PMIC could do that in that timeframe, but there are plenty of PMICs today with multiple 1Amp DC/DCs like the DA9052. Are we really talking more than 900mW for a single core?

At 3GHz on HPM? I'd say well above. Hell, Scorpion came to about that much at 45LP at 1.9GHz when running something like Saxby.

Either way, significantly more powerful PMICs already exist, like the WM8326. You could even handle a quad-core A15 with that thing: 2.5A for the 'peak' core, 2.5A for the other 3 cores, 1A for the rest of the system, 1A for I/O. Then you'd need a separate power subsystem for the DDR3, but that's pretty much par for the course anyway.

All this is adding up to quite a bit.

Just to be clear, we're not talking about 3W TDP for the CPU alone, we're talking about peak power with aggressive thermal throttling resulting in probably a 1W TDP max for the CPU and 1.5W for the full SoC. And that's for a quad-core A15 (NVIDIA Logan?) obviously the majority will be a much more reasonable dual-core.

I'm curious where you get those numbers from. Do you really expect a 3GHz A15 on 28HPM to consume roughly the same power as a 1.5GHz A9 on 40LPG?

 

[Arun]

It isn't quite as neat as that. HPM is inherently orders of magnitude more leaky than bulk for the same CMOS configuration, temperature, voltage and process. Yes, if you rework all of your gate structures and size your channels such that the leakage is lower, you can still achieve higher frequencies than with high-frequency bulk-Si designs but you'll never really quite reach the power levels a low-profile LP design will. Simply put, a low-power LP design, while a lot slower, will still provide a sizable (2-4x from the last library models I've seen from TSMC) reduction in static current but at the cost of significantly less frequency headroom.

Hmm. But what Vt are we comparing here? My point is that 28HPM has a 'Ultra High Vt' option which according to TSMC has the same leakage as 28LP Standard Vt. Here's a public quote on it:

TSMC also provides a 28nm high performance for mobile applications (HPM) technology to address applications requiring both high speed and low leakage power. The 28nm HPM process provides faster speed than 28HP with leakage power similar 28LP. With such wide performance-to-leakage coverage, 28HPM is the process of choice for devices targeting networking, tablet, and mobile consumer product applications. Risk production is scheduled for late 2011.

There's also the fact that 28HPM is at 0.9v while 28LP is at 1.05v so this (among other things) should result in lower dynamic power consumption for the same frequency (more than compensating other factors)

I suppose you could get away with only Standard Vt on 28LP to reduce costs whereas there's no way anyone will not use Multi-Vt on 28HPM. But that's another point that indicates 28LP vs 28HPM is mostly an economic decision.

I don't know how realistic the type of fine-grain control you speak of is.

Well, Louis Tannyeres of ST-Ericsson assured me they were already doing all that stuff on the A9600 (and not just for the CPU) so unless he was horribly mistaken, I think it's quite realistic It's possible that some companies will try to reach these crazy frequencies without smart enough power management, but then they're in for a rude awakening.

To me, if a device can't at least handle some type of sustained task at its peak performance, it doesn't belong there. I seem to be the minority in that though....

Oh, I think dual-core 2.5-3GHz A15 makes a lot of sense, but I agree that a quad-core 2.5GHz+ A15 is ridiculous overkill and it doesn't belong in the 28nm generation. If it happens (with heavy throttling), it will be for marketing reasons, not technical ones.

At 3GHz on HPM? I'd say well above. Hell, Scorpion came to about that much at 45LP at 1.9GHz when running something like Saxby.

Ouch. Yes, I suppose peak power can be much higher than average power, and average CPU power is already higher in handhelds than many people realise. I see your point now.

I'm curious where you get those numbers from. Do you really expect a 3GHz A15 on 28HPM to consume roughly the same power as a 1.5GHz A9 on 40LPG?

I'm inventing them in this specific case but I thought I made it relatively clear they were ridiculously rough estimates. Don't worry, I'm not a big fan of made up estimates and would rather not overuse them...

More importantly, I'm NOT saying a 3GHz A15 on 28HPM will take the same power as a 1.5GHz A9 40LPG. Of course it will be much higher. But I do claim that a *single* 3GHz A15 core on 28HPM will take less power than *four* A9 cores on 40LPG. I think that's a pretty safe assumption

 

[metafor]

Hmm. But what Vt are we comparing here? My point is that 28HPM has a 'Ultra High Vt' option which according to TSMC has the same leakage as 28LP Standard Vt. Here's a public quote on it:
There's also the fact that 28HPM is at 0.9v while 28LP is at 1.05v so this (among other things) should result in lower dynamic power consumption for the same frequency (more than compensating other factors)

I'm looking at the numbers from SPICE on the latest models and while I can't give specifics, UHVT only becomes equal at larger transistor widths and its delay is about the same as LP SVT. Needless to say, a 3GHz CPU will not be using much of UHVT cells. HVT is about 20x leakier with 50% of the delay and it gets progressively worse from there.

Like I said, marketing

Well, Louis Tannyeres of ST-Ericsson assured me they were already doing all that stuff on the A9600 (and not just for the CPU) so unless he was horribly mistaken, I think it's quite realistic It's possible that some companies will try to reach these crazy frequencies without smart enough power management, but then they're in for a rude awakening.

I'm not questioning whether or not it's conceivable, I'm questioning whether such aggressive power management negates the point of having these high frequency chips to begin with; short of just for marketing/benchmark reasons.

Oh, I think dual-core 2.5-3GHz A15 makes a lot of sense, but I agree that a quad-core 2.5GHz+ A15 is ridiculous overkill and it doesn't belong in the 28nm generation. If it happens (with heavy throttling), it will be for marketing reasons, not technical ones.

You could conceivably get away with a dual 3GHz A15 in a tablet form factor but again, that's a lot of heavy throttling. Way more than what you see in current SoC's.

It will have to be throttled too much to make a difference. But it doesn't cost that much extra silicon on a 90mm² SoC and it's a great marketing gimmick, so I expect it will happen anyway.

Sadly, I think you're right.

More importantly, I'm NOT saying a 3GHz A15 on 28HPM will take the same power as a 1.5GHz A9 40LPG. Of course it will be much higher. But I do claim that a *single* 3GHz A15 core on 28HPM will take less power than *four* A9 cores on 40LPG. I think that's a pretty safe assumption

In a full-bore scenario, perhaps. But in realistic workloads, even without asynchronous core management, the quad-A9 would be far lower in power consumption. A15 isn't just running a lot faster on leakier transistors, the microarchitecture is also gigantic compared to A9.

 

[stiftl]

...was under the impression Wayne was A15 based... did I miss something?

I thought that Wayne was just a die shrinked Kal El?

 

[Ailuros]

I'd personally expect from 28/32nm and onwards GPU blocks to capture a far bigger portion of the SoC die estate than up to now. In that regard if I am to call a SoC high end I'd expect a high end CPU as well as a high end GPU. It'll be interesting what Adreno3xx will bring to the table.

Arun,

Another OT: since there are many factors that are out of NV's control, forecasts can end up more than often optimistic. What I'd be interested in to read here would be a separate thread about Google Android and its future aspects. I'm afraid that overall we're putting way too much weight on hardware and way less on software ecosystems; in reality both are equally important.

 

[Arun]

I'm looking at the numbers from SPICE on the latest models and while I can't give specifics, UHVT only becomes equal at larger transistor widths and its delay is about the same as LP SVT. Needless to say, a 3GHz CPU will not be using much of UHVT cells. HVT is about 20x leakier with 50% of the delay and it gets progressively worse from there.

Like I said, marketing

Thanks for the rough data! 20x for HVT is a lot more than I expected, and I didn't expect UHVT to *also* require larger transistor widths (long channels I presume) to be equal to 28LP SVt, so I see your point. I suppose 28HPL would be better at High Vt but doesn't even have a Ultra High Vt option so probably not that great either.

Obviously this is not the Vt used for 3GHz CPUs, but the question was whether High-K was fundamentally unsuitable for handhelds chips. So I could be missing something, but while 28HPM UHVT is very slightly worse than 28LP SVT in terms of performance-per-unit-of-leakage, aren't we still comparing 0.9v versus 1.05v? While some other factors may result in higher power consumption with 28HPM, 150mV lower voltage is a pretty massive difference, so I'd certainly expect dynamic power consumption to be (noticeably) lower. Even if I'm wrong (?!) surely it can't be higher.

Either way, I don't see how 28HPM is fundamentally unsuitable. It is definitely more expensive, and if you don't need the speed you really don't gain that much so it's a complete waste, but it still looks like more a question of economics than engineering if "UHVT only becomes equal at larger transistor widths and its delay is about the same as LP SVT"... Then again I suppose economics is the most important factor anyway and it's madness to dissociate it.

I'll say one thing though: Icera's ICE9000 baseband (up to 150Mbps LTE) is on 28HP (not HPM!) Standard Vt with long channels. I suppose some people just like that extra bit of challenge Of course, they can only do that because they can shut down the core DC/DC for the entire chip for very long periods of time (>1s iirc) on standby. An application processor can't really do that.

I'm not questioning whether or not it's conceivable, I'm questioning whether such aggressive power management negates the point of having these high frequency chips to begin with; short of just for marketing/benchmark reasons.

I honestly don't think it does. Remember that web browsing is arguably the most important benchmark on a smartphone, and it's VERY bursty. Also effectively 'turbo'-ing a single core is very useful for workloads which are still single-threaded (the vast majority).

There is one obvious trade-off which is much higher leakage, so these cores are horribly inefficient when working on a task that shouldn't require more than several hundreds MHz. And that's a big problem, which is why ST-Ericsson uses heterogeneous computing (don't know the specifics but I'd expect something along the lines of a 1GHz A9).

In a full-bore scenario, perhaps. But in realistic workloads, even without asynchronous core management, the quad-A9 would be far lower in power consumption. A15 isn't just running a lot faster on leakier transistors, the microarchitecture is also gigantic compared to A9.

Hmm, that's true. If we're only comparing TDPs and the quad-A9 is allowed to go all-out then it's lower, but average power would still be higher in the real world.

 

[Arun]

I'd personally expect from 28/32nm and onwards GPU blocks to capture a far bigger portion of the SoC die estate than up to now. In that regard if I am to call a SoC high end I'd expect a high end CPU as well as a high end GPU. It'll be interesting what Adreno3xx will bring to the table.

Now consider that each mm² of GPU silicon takes more memory bandwidth than each mm² of CPU silicon and that memory bandwidth isn't even scaling as fast as Moore's Law. A few guesses on possible consequences: increasing memory bus widths, increasing ALU-TEX ratio, AF still not viable.

Another OT: since there are many factors that are out of NV's control, forecasts can end up more than often optimistic. What I'd be interested in to read here would be a separate thread about Google Android and its future aspects. I'm afraid that overall we're putting way too much weight on hardware and way less on software ecosystems; in reality both are equally important.

Well, you can start threads too you know! For a topic like that, you don't even really need to come up with a good first post, just a good title.

 

[Ailuros]

Now consider that each mm² of GPU silicon takes more memory bandwidth than each mm² of CPU silicon and that memory bandwidth isn't even scaling as fast as Moore's Law. A few guesses on possible consequences: increasing memory bus widths, increasing ALU-TEX ratio, AF still not viable.

You wouldn't want me to address the first as I'd go further off-topic. ALU:TEX ratio will increase anyway as it'll most likely increase on the ULP GF too in T30, albeit I know out front that you'd disagree. As for anisotropic I still can't figure out why developers opted for iPad2 application adjustments for MSAA and higher resolution textures for instance and neglected AF. I fail to understand why for instance 4xAF would had hurt significantly system performance there.

Well, you can start threads too you know! For a topic like that, you don't even really need to come up with a good first post, just a good title.

You're a far worse perfectionist than I am when it comes to stuff like that. Look who's talking

 

[metafor]

Obviously this is not the Vt used for 3GHz CPUs, but the question was whether High-K was fundamentally unsuitable for handhelds chips.

Oh no, one can design around the rather large leakage/switching current of high-k with different gate structures and sizing. The resulting power will still be higher even at the same frequency compared to a 28LP design but if done correctly, it shouldn't be significantly higher and frequency headroom should be significantly higher without needing to increase voltage.

I simply said a 3GHz multi-core CPU may be too much even for a tablet without aggressive throttling.

So I could be missing something, but while 28HPM UHVT is very slightly worse than 28LP SVT in terms of performance-per-unit-of-leakage, aren't we still comparing 0.9v versus 1.05v? While some other factors may result in higher power consumption with 28HPM, 150mV lower voltage is a pretty massive difference, so I'd certainly expect dynamic power consumption to be (noticeably) lower. Even if I'm wrong (?!) surely it can't be higher.

UHVT Isat at minimum pitch is about the same as 28LP SVT. But as the pitch (width) scales a bit higher, HPM's Isat increases significantly. Overall switching current for UHVT seems to be low enough. HPM-HVT compared to 28LP-SVT seems to be about 2x the current despite being at a lower voltage. You have to keep in mind, metal gates are inherently higher current devices.

I honestly don't think it does. Remember that web browsing is arguably the most important benchmark on a smartphone, and it's VERY bursty. Also effectively 'turbo'-ing a single core is very useful for workloads which are still single-threaded (the vast majority).

There is one obvious trade-off which is much higher leakage, so these cores are horribly inefficient when working on a task that shouldn't require more than several hundreds MHz. And that's a big problem, which is why ST-Ericsson uses heterogeneous computing (don't know the specifics but I'd expect something along the lines of a 1GHz A9).

I don't know how realistic one can point to page rendering as a true bottleneck even on a smartphone these days. Arguably, we've reached that cusp where page loading is once again limited by network delay. I'd say the future of performance for a smartphone would be applications such as AR and on-the-fly image processing; all of which aren't very "bursty" tasks.

I absolutely agree and love the idea of heterogeneous processors. However, the problem is that the OS needs to be intelligent enough to schedule tasks well. So far, I've not seen any indication that this is true under Android.

Hmm, that's true. If we're only comparing TDPs and the quad-A9 is allowed to go all-out then it's lower, but average power would still be higher in the real world.

I'm not sure I understand that conclusion. The quad-A9 in realistic workloads will likely remain mostly idle save for one core. Even if each core scaled up to 1.5GHz briefly due to lack of asynchronous control. The single-core A15 going up to 3GHz would still dwarf that in power consumed for a given task.

A 28LP 1.5GHz A15, on the other hand, is a different story.

 

[Rys]

On-topic for the thread but off-topic for the recent side conversation, MSM8x60 is now shipping in retail devices (HTC Sensation notably).

 

[Arun]

Oh no, one can design around the rather large leakage/switching current of high-k with different gate structures and sizing. The resulting power will still be higher even at the same frequency compared to a 28LP design but if done correctly, it shouldn't be significantly higher and frequency headroom should be significantly higher without needing to increase voltage.
[...]
You have to keep in mind, metal gates are inherently higher current devices.

Hmmm. Maybe I'm reading too much into what you said, but it seems to me that "frequency headroom without needing to increase voltage" is really just "wasted power" since you could lower the voltage instead unless you're at the voltage floor. And while I agree that power at the voltage floor is an important criteria, it's certainly not the only one. I think we need to make a distinction between power/transistor and power/performance.

Anyway I can see that my original points are very diminished already! I very much appreciate the discussion.

I don't know how realistic one can point to page rendering as a true bottleneck even on a smartphone these days. Arguably, we've reached that cusp where page loading is once again limited by network delay.

Of course nobody's asking for miracles on a HSPA pipe at peak hour, but the majority of smartphone internet traffic is still done on WiFi AFAIK, and that's mostly limited by the wireline network itself.

I'd say the future of performance for a smartphone would be applications such as AR and on-the-fly image processing; all of which aren't very "bursty" tasks.

True, same for gaming. There are many applications where this burst headroom is completely pointless. Doesn't mean it's useless for everything though, and it certainly doesn't mean marketing drones will start advertising that fact anytime soon.

I absolutely agree and love the idea of heterogeneous processors. However, the problem is that the OS needs to be intelligent enough to schedule tasks well. So far, I've not seen any indication that this is true under Android.

I asked ARM about this, and they basically said "for now, OS support is up to the SoC vendor". Also, most importantly, my expectation is that the first implementations will be 'either or' - you won't be able to have the A5/A9 on at the same time as the A15. That should simplify things significantly.

I'm not sure I understand that conclusion. The quad-A9 in realistic workloads will likely remain mostly idle save for one core. Even if each core scaled up to 1.5GHz briefly due to lack of asynchronous control. The single-core A15 going up to 3GHz would still dwarf that in power consumed for a given task.

Actually, I meant to agree with that, heh I tried pointing out that peak power would still be equal or lower, so if one solution doesn't strictly need thermal throttling then the other doesn't either, but that's a very secondary point (especially as I'm not 100% convinced T30 can get away without real thermal throttling). I agree that average power is more important.

---

Rys: You know me, it would be awkward if we had to ban people for going off-topic too regularly! And oops, I didn't notice the HTC Sensation used the MSM8x60, that's very nice.

 

[Ailuros]

On-topic for the thread but off-topic for the recent side conversation, MSM8x60 is now shipping in retail devices (HTC Sensation notably).

Dunno it it's been posted before:

http://www.glbenchmark.com/compare....Sensation&D2=Asus EP71 Eee Pad&D3=Malata Zpad

The Sensation is at 960 while the latter two at 1024. Not bad at all for the Adreno220, but nothing to write home about against Tegra2 either. Just a gut feeling but judging from the 220 low level results there might be some additional headroom for further driver improvements.

 

[metafor]

Hmmm. Maybe I'm reading too much into what you said, but it seems to me that "frequency headroom without needing to increase voltage" is really just "wasted power" since you could lower the voltage instead unless you're at the voltage floor. And while I agree that power at the voltage floor is an important criteria, it's certainly not the only one. I think we need to make a distinction between power/transistor and power/performance.

It's not quite as simple. The voltage/delay curve is non-linear. For instance, dropping from 0.81V (standard voltage for HPM) to 0.7V ("low" corner) increases delay by almost 10x. The dynamic current does not drop by 10x, though. Increasing voltage to, say, 0.9V doesn't increase delay by 10x but does increase dynamic current by a few orders of magnitude. For any given process and logic-gate structure, there is a sorta "sweet spot" where you get the most gain in delay for the least power increase.

If there is frequency headroom without having to increase the voltage beyond the mid-curve, then it is well worth it.

 

[Wishmaster]

Is it possible at that timeframe? A15 class CPU and at 28nm sampled before any other. Can't wait to see if they manage to do this. http://androidandme.com/2011/05/new...next-month-28nm-chip-promises-75-lower-power/
Wonder if they'll show some working prototypes(just like nvidia did with kal-el) at computex...

 

[Erinyes]

Is it possible at that timeframe? A15 class CPU and at 28nm sampled before any other. Can't wait to see if they manage to do this. http://androidandme.com/2011/05/new...next-month-28nm-chip-promises-75-lower-power/
Wonder if they'll show some working prototypes(just like nvidia did with kal-el) at computex...

A bit late but I'd imagine they'll be showing it off at CES next year, dont think there'll be an opportunity before that.

Btw does MSM8960(or APQ8064) retain the ascynchronous CPU architecture introduced in MSM8260/8660?