PSX 90nm issue - Chipworks gives their opinion

[passerby]

Whatever happened to the original thread. No, don't answer. Anyway here are Chipworks' opinions.

http://www.chipworks.com/news/11SonyPSX.htm

 

[London Geezer]

:| ...Who to believe.... :|

 

[MfA]

Kinda depends on the motivation, if they are just doing this to attract attention for their reports I can understand the fact that they pick out one feature of the chip and dont mention other design rules at all ... they might not have done much work on the chip yet, and they want to keep the best information under wraps.

On the other hand, if Sony payed them money the fact that they picked only the gate length would probably mean the process misses the the mark on nearly everything else.

 

[Guden Oden]

Why does anyone even care?

A chip is a chip is a chip, and it won't run any faster or better no matter what process it uses if all other factors are the same.

Anyone griping over this "controversy" is just doing exactly that. Grow up and get over it, okay?

 

[passerby]

Why does anyone even care?

A chip is a chip is a chip, and it won't run any faster or better no matter what process it uses if all other factors are the same.

Ah, but most of us know this already, and you are correct that most of us do not care. However the sticking point for several of us is not whether it runs faster or better, but whether it was a blatant lie to customers and investors. (Admittedly most customers won't care actually)

It appers that the "classification" of the chip is a subjective topic(at least to an "outsider" such as myself). Though personally I find Sony, Toshiba and Chipworks' explanations quite reasonable. asicnewbie made some valuable comments in the previous thread, and Chipworks seems to go somewhat on a similar track. After all if we go by the first report's classification guidelines, then Intel also didn't announce a 90nm device in last Fall's Intel Developer Forum.

 

[Guden Oden]

Why should anyone here care wether it's a blatant lie or not?

GODS!

This is a typical 'b*tch and moan' type of topic to which f*nboys of all colors tend to home in on. It's not productive.

 

[Deadmeat]

...

Look at the power consumption rating of 90 nm PPC970FX; 60 watts each at 2.4 Ghz. Throw in Intel's long-running trouble with 90 nm Prescott and the outlook of whole future sub-90 nm process generations doesn't look so good.

CELL was built on the promise that the transition to sub-90 nm generation would be smooth and easy way back in 2001. Now this prediction turned out to be wrong and the whole chip fabricating industry is struggling to make 90-nm process work correctly and yield acceptably. Should the transition to 65 nm process falter, SCEI is hit directly since CELL depends on the availability of 65 nm process.

Unlike low-clocking PSX2OAC and PSP, Cell will be pushed to its design limit and run into very trouble that has dogged Intel and IBM for past year. Can SCEI beat these challenges? Only time will tell.

 

[MfA]

Guden Oden talking about games isnt productive either (if you dont care talking about that either, and neither about future hardware and issues which relate to it then you shouldnt be here). It might seem more rational to you as a way of informing yourself of games you might enjoy ... but while discussing future hardware isnt done because in and of itself any information gleaned is relevant to our enjoyment of that hardware, the discussion in and of itself is the game to us.

You have your games, we have ours ... neither is productive. Shoo go stare at your pixelated warriors, and your discussions about them, and we will play our own games. Noone is forcing you to participate. Dont whine about whining, because I will just be forced to do the same ... and that way lies madness.

 

[Panajev2001a]

Re: ...

Look at the power consumption rating of 90 nm PPC970FX; 60 watts each at 2.4 Ghz. Throw in Intel's long-running trouble with 90 nm Prescott and the outlook of whole future sub-90 nm process generations doesn't look so good.

CELL was built on the promise that the transition to sub-90 nm generation would be smooth and easy way back in 2001.

I see the transition to sub-90 nm manufacturing processes enjoying one particular and hopefuly positive fact: it started after the initial problems with the 90 nm technology clearly surfaced.

A lot of people working on then ultra-bleeding edge 90 nm manufacturing processes did not expect gate leakage ( passive power ) to be such a nasty problem: it passed many people's expectations.

The work started on sub-90 nm technology has all that experience behind it and all the work done so far to minimize leakage.

The outlook could look better, but it is not horrible and tear inducing ( not yet hopefully ).

Deadmeat, do you know that the latest rumors are that the PowerPC CPUs in Xbox 2 will use 65 nm technology ( ATI might also ship them a 110-90 nm GPU and MS could get a third party foundry to shrink the chip down to 65 nm [with some help/input from ATI] ) ? I think you know that.

 

[nondescript]

Re: ...

CELL was built on the promise that the transition to sub-90 nm generation would be smooth and easy way back in 2001. Now this prediction turned out to be wrong and the whole chip fabricating industry is struggling to make 90-nm process work correctly and yield acceptably. Should the transition to 65 nm process falter, SCEI is hit directly since CELL depends on the availability of 65 nm process.

Unlike low-clocking PSX2OAC and PSP, Cell will be pushed to its design limit and run into very trouble that has dogged Intel and IBM for past year. Can SCEI beat these challenges? Only time will tell.

Funny you should say that...

http://www.eedesign.com/showArticle.jhtml?articleID=17601973

Optimism surfaces on the road to 65 nm
By Ron Wilson
EE Times
February 05, 2004 (11:00 AM EST)

SANTA CLARA, Calif. — Engineering managers from the equipment, foundry, IDM and EDA remain optimistic about the prospects for eventual production at the 65-nm process node — a markedly different assessment from the view many held of 90 nm at this stage of its development.

Greg Spirakis, Intel Corp.'s vice president and director of design technology, cited growing density, growing challenges but an unshakable belief in the efficacy of Moore's Law. Still, Spirakis acknowledged the cost of continued progress was getting higher.

Ashok Sinha, senior vice president of the Silicon Business Sector at Applied Materials, endorsed Spirakis' view. "The barriers to Moore's Law are economic, not technical," he said. On the technical side, Sinha suggested that the move from 90 nm to 65 nm would be less disruptive than the move from 130 to 90 has been. "Between 90 and 65, the changes are driven by power issues," he said, adding that the differences would be the introduction of high-K materials for gate dielectrics and of strained silicon for the channel.

"These are still major changes," Sinha said. "They bring with them cost risks, cycle-time risks and the risks that always come with integration of new materials into a working process."

John Yue, vice president of technology at TSMC North America, struck an even more optimistic note. "A few years ago, 65 nm looked daunting," he said. "Today, it looks very doable. The issues we have to solve are still leakage and signal integrity: the same as we are facing today with 90 nm, just harder."

Yue agreed that high-K dielectrics and metal gates could be "an option" for 65-nm production.

Charles Rothschild, R&D manager of the Automated Test Group at Agilent Technologies, was more cautious. "A new technology stands on three legs," Rothschild said, "Silicon technology, integration technology and an application that can use the advances in volume. When these three converge, we get a huge spike in semiconductor demand."

Rothschild said technology and integration — that is, packaging and assembly — issues were in hand, but a "killer application" has yet to emerge. "Historically, manufacturers are only willing to pay a fixed fraction of total manufacturing cost on test. But test doesn't scale with Moore's Law. We are doing everything we can to keep test cost from busting the budget."

Rothschild described how test engineers have been implementing multisite testing, pushing BiST to the limits, and building concurrency and high-bandwidth test-mode I/O on top of BiST to try to force test times down.

Antun Domic, senior vice president and general manager at the Synopsys Nanometer Analysis and Test division, warned: "The scariest thing to me is the sheer amount of data we are generating with these designs." He cited explosions in RTL code size — with 1 million lines of RTL not unreasonable for a moderate-sized 65-nm chip — and the inextricable intertwining of verification data and design-for-yield data into the design data set.

Bhusan Gupta, director of the Innovative Systems Design Lab at ST Microelectronics, agreed that design reuse and higher levels of abstraction must be employed to reduce design complexity. He also e warned that the leakage problem was far from simple.

"The leakage current on one of these chips is so temperature-dependent that it can change by a factor of 15 between a cold chip at start-up and a chip at operating temperature. You have to deal with that wide a range in the design flow, not as an afterthought," Gupta said.

So the industry consensus seems to be that 130->90 is much harder that 90->65 will be.

Notice that the main barrier, as stated by Sinha of Applied Materials, is economic, not technical. This directly ties in to cthellis' excellent post on why even though Sony/Toshiba has 90nm technology, they chose to use it only when it would cut cost, because the EE+GS chip does not require higher performance.

This view is echoed by Rothschild of Agilent, who says that the process technologies were well in hand, just waiting for the killer application. PS3 sounds like a killer app to me.

In short, it will be an engineering challenge to get there, but the problems surmountable. The tough part seems to be getting to 90nm, going to 65 will be much easier.

 

[jvd]

Why should anyone here care wether it's a blatant lie or not?

GODS!

This is a typical 'b*tch and moan' type of topic to which f*nboys of all colors tend to home in on. It's not productive.

Sorry but this is one of the dumbest things I've ever heard.

Your saying we shouldn't care that we were lied to . You say its not big deal. I ask what is next . THey lied about this . Why wont they lie about something else ? ANd if no one cares about it this time mabye next time it will be a bigger deal . Mabye next time they will lie about a console performance . Or mabye something else .

This is an important topic. The truth is important . I don't care for being lied to .

 

[Guden Oden]

Jvd,

What are you buying a PSX for, because it's got an EE+GS chip made with .09u tech? Jesus, no!

Why would you even care what tech is used to manufacture the chip? It's neither faster nor better in any way! It'll work just the same as the original .25u EE and GS chips did.

The reason this is a whine topic - and this ties in with what Mfa moaned about - is because *none* of us are qualified to speak out on the topic. We are either uneducated on the subject, lacking formal training and experience in CMOS design, or having that, we lack an EE+GS@90nm chip and an electron microscope. All that remains to do is speculate, whine and b*tch, and that is what I call not productive.

At BEST, we can regurgitate what other, better informed people have already said (which is pointless I might add, as anyone can parrot someone else, doesn't mean we actually know what we're talking about or have anything original to say), but mostly it will either be the above regurgitation colored by a healthy dose of f*nboy influence, or it will be pure speculation, conjecture, supposition and make-belief. All driven by the same f*nboy motives btw. *cough* Read: DM *cough*

So this is IMO a BS topic that will lead nowhere.

 

[jvd]

I disagree. I find the only one whining is you .

It doesn't matter if the chip is .32 . What matters is they lied . IT doesn't matter if it gives the same performance. They lied .


That is what you don't seem to get .


While most of us might not be able to comment on this . there are some that can and using articles posted by those that can we can learn the truth.

And the truth is whats important .

 

[Geeforcer]

So this is IMO a BS topic that will lead nowhere.

Then leave.

 

[Deadmeat]

...

So the industry consensus seems to be that 130->90 is much harder that 90->65 will be.

We won't know until the 65 nm test fab begins, won't we? Current leakage problem gets worse, not better, as the geometry shrinks, and not even SOI can do much about it. In the mean time, let 100 watt 90 nm processors roll in..

This directly ties in to cthellis' excellent post on why even though Sony/Toshiba has 90nm technology, they chose to use it only when it would cut cost, because the EE+GS chip does not require higher performance.

Then what happens when SCEI tries to fabricate an all 90 nm node device like PSP ASIC? Massive current leakage? Low yield? What will happen when the first CELL@90 nm prototype is demonstrated this spring?

What are you buying a PSX for, because it's got an EE+GS chip made with .09u tech? Jesus, no!

It is an invester issue, not a product issue. Sony promised that its fab was the best and most advanced in the industry, it turned out to be not true.

If I were the president of Sony, I would not have claimed that PSX2OAC was a 90 nm product. For all purpose and intentions, it does not even deliver the benefits of a true 90 nm process, the transistor density as witnessed by 150 million transistor Dothan.

Why would you even care what tech is used to manufacture the chip?

Because it is the same technology to manufacture CELL and PSP.

 

[Panajev2001a]

If I were the president of Sony, I would not have claimed that PSX2OAC was a 90 nm product. For all purpose and intentions, it does not even deliver the benefits of a true 90 nm process

It does deliver what Sony wanted: a small, very small and cheap EE+GS processor with minimal power consumption that also tried out their new 90 nm process and deep trench capacitor e-DRAM ( the whole GS core, which is not ultra small, was shrunk to 90 nm ).

You are always overly negative about Sony... let's strike a middle ground here, ok ?

 

[Vince]

Re: ...

Because it is the same technology to manufacture CELL and PSP.

What I find most hilarious is your ongoing attempt to discredit STI's move to 65nm, yet you never question that Microsoft's IC will most likely launch in 65nm and in 2H2005.

Something just doesn't add up to me.

It is an invester issue, not a product issue. Sony promised that its fab was the best and most advanced in the industry, it turned out to be not true.

Well, are we selectivly reading or readinf different reports because I see:

Chipworks[/url]]In addition the Sony device uses an advanced two stack low-k dielectric structure. The combination of this dielectric process and the smallest transistor seen so far by Chipworks makes this one of the most advanced processes in volume production today.

 

[Guden Oden]

I disagree.

Why?

What meaningful information have you contributed that was not already available from other sources?

I find the only one whining is you .

Rofl, you have a fairly unique definition of "whining". I am stating an opinoon based on fact, that does not qualify as "whining".

What matters is they lied .

They DID? Who's saying that? Based on WHAT? Neither of the two reports quoted in this or the other locked threads said that Sony was lying.

That is what you don't seem to get .

Oh, I get when someone wants to whine and b*tch, alright.

And the truth is whats important .

We do seem rather far from it in this thread, however.


And Geeforcer:

Grow UP, will you?

 

[PiNkY]

I suppose Deadmeat definitely has a point when he emphasises the ever increasing difficulities of process migration. Whether the step from 90nm to 65nm will be as "rocky" as the one from 130nm to 90nm remains to be seen (some engineering manager from a company, whose business model heavily relies on smooth process transition, stating he's hitherto optimistic regarding the migration doesn't mean a whole lot to me). Regarding ee+gs, i think it's quite irrelevant that not all parts of the ic were redone to meet 90nm specs as it is hardly a high end ic nowadays anyway and the primary reason for the die shrinks and integration is (total) cost reduction (redesign engineering costs + a function of die size and yield rate, etc.) and not having a process testbed for Cell. Also comparing Sony's "process prowess" to Intel's by comparing a 300 MHz ic to a 3GHz one seems moot to me. I am also of the opinion that, contrary to deadmeat's statements, a scalable architecture (such as cell) is much better suited towards unforseen difficulities in process migrations then single monolithic designs (STI might just opt for going with a PE less when the chips are down (same goes for MS & Nintendo), while... does anyone remember Intels major redesign of the original p4 core, when they realized, that their expected process capabilities would be lower then previously anticipated).

 

[Dave Baumann]

And Geeforcer:

Grow UP, will you?

I think he was suggesting you leave the thread - and I would agree with him. If you don't like this thread then stop commenting. Given the importance people place on process (quite correctly) and the number of links from people in this forum I've previously seen on Sony being the the first to deliver 90nm processes, discussions on how that is achieved and whether we are comparing process apples to process apples is a viable and relavent discussion.