Philips Semiconductors beats everyone to 65nm!

PC-Engine

Banned
http://www.eetimes.com/semi/news/OEG20030912S0058

We're able to deliver 120-nm products shipping today to customers, we have prototypes now at 90-nm to customers and we'll be able to have 65-nm products this year, first silicon," McGregor said. "We're ramping up right now in 300-mm wafers in the Crolles pilot line. It's going very well," he added.

Another Crolles executive has reportedly said he expects to have first production of a 65-nm product at the end of 2004. That still puts the Crolles-2 partners ahead of the International Technology Roadmap for Semiconductors.
 
Re: ...

DeadmeatGA said:
Does Phillips's first sillicon have half a billion transistors like some members of this board are expecting??

Considering that article links not a speck about the products they're bringing out on 65nm, isn't it impossible to say anything one way or another?
 
Does Phillips's first sillicon have half a billion transistors like some members of this board are expecting??

The half billion ( 500 million ) transistors for PlayStation 3 CPU originates from the annoucement of Emotion Engine 3 / EE3 back in 1999, by Sony.

that estimate was a long, long time ago, and I am expecting three quarters of a billion transistors now, for the CPU alone, if not more.

Of course, the entire PS3 should meet or exceed 1 billion transistors :)
 
I wasn't aware it was a race. :LOL:

Anyway, somebody please wake me up when Phillips launches their kickass games console based on .65nm tech with widespread industry support... *yaaaawwwwnnnnnn*


*G*
 
Lol......well I always thought Phillips was more capable than people gave them credit for, but it's been awhile since they've been interested in consoles. Maybe microsoft might pick them to fab something, if they have the capability to do so, but I don't see them doing anything this gen since the systems are basically fully planned out by now.
 
It is always a race, although maybe not entirely relevant for this board. Apart from consoles Philips and Sony are very simular companies. If Sony could get high yields on 65nm chips and get lower costs per function sooner than Philips they would have a competetive advantage ... it seems that wont be a problem for Philips.
 
This is great news for MS who's purchasing IP from ATI considering TSMC is also involved ;)

Could this pave the way for MS to push transistor budgets???

Crolles-2 is a research and pilot manufacturing facility that Philips shares with and STMicroelectronics and Motorola's Semiconductor Product Sector.

Crolles-2 has been working with Taiwan Semiconductor Manufacturing Company Ltd., the world's leading foundry and a close affiliate of Philips, on 90- and 65-nm manufacturing process technologies.
 
This was really below my radar ... I was wondering when Phillips Semi got so good...but then I read the line that said it was a joint effort with STM and Motorola, and it makes a lot more sense now.

Sweet! 65nm, with TSMC process compatibility. It seems to me (the article doesn't say it, but the sense I get) that TSMC is only an interested partner, letting the other three, with better R&D, figure out the process stream, and TSMC using whatever the pilot line figures out. The other three get to develop their process, knowing that it will be used by the largest foundry, and that their process won't be ignored - assuring themselves that their own production lines can use this process without being left in the cold.

Now lets's see what STI can cook up.
 
nondescript said:
Now lets's see what STI can cook up.

I would think they've already cooked theirs up, right now they're just letting it simmer until it gets JUST right. :LOL:

*G*
 
PC-Engine said:
This is great news for MS who's purchasing IP from ATI considering TSMC is also involved ;)

How so? This tells us absolutly nothing of what the actual process entails. In fact, this is quite shady as they didn't release any of the process specifications - as STI did - which reminds me of this article:

[url said:
http://www.eetimes.com/story/OEG20030818S0048[/url]]Chris Progler, the chief technology officer at mask vendor Photronics, was at Semicon West a few weeks ago, and I asked him which form of lithography might be used at the 32- and 22-nanometer nodes. Progler, who once managed IBM's optical-lithography development, laughed and said he thought the whole idea of "nodes" on the road map would "diffuse away" after the 65-nm generation.

Progler backed up his argument at a lithography seminar, organized by Dai Nippon Screen, saying that he has taken 10 so-called 90-nm devices, looked at the masks and discovered "enormous ground rule differences" among them.

The minimum half-pitch on the 10 logic chips ranged from 110 to 170 nm, Progler said, with none of them having a 90-nm feature anywhere. That drew a chuckle from his audience, as if Grandma had caught a few hands in the cookie jar.

This is important for several core issue beyond the typical, "Hey, Look! I can do that too!!" mantra that so many believe in here. For example, when Sony and Toshiba unveiled their 65nm embedded process - they supplied hard data which showed us that they're process is 20-30% smaller than NEC's comperable technology. Thats an entire node shrink right there - within the so-called same "process"!! When STI or IBM independently talks of their xS process and the benefits of (s)SOI or their dielectrics - they give numbers which show us they're ahead of the industry curve.

This release presented nothing, nor can I find anything on it. Which leads me to believe, as I stated before, that this is a PR "Hey, me too" announcement.
 
:oops:

EDIT: I took away the "#&^$ you, I'm going to eat your children and bash the %&#* out of you with my Aluminum Bat and then pee on you" - when the smilies loaded. j/k, was a :oops: all along. Oh well, so much for me compilementing your butt anymore ;)
 
This is important for several core issue beyond the typical, "Hey, Look! I can do that too!!" mantra that so many believe in here. For example, when Sony and Toshiba unveiled their 65nm embedded process - they supplied hard data which showed us that they're process is 20-30% smaller than NEC's comperable technology. Thats an entire node shrink right there - within the so-called same "process"!! When STI or IBM independently talks of their xS process and the benefits of (s)SOI or their dielectrics - they give numbers which show us they're ahead of the industry curve.

Actually STI hasn't shown hard evidence until they've made a working chip using 65nm ;)

Also we're talking about logic here not eDRAM so the 20-30% eDRAM macro size advantage over NEC's is irrelevent with regards to Phillips/TMSC 65nm process capabilities. And if ATI's Xbox VPU doesn't have eDRAM then it's back to back irrelevent...
 
PC-Engine said:
Actually STI hasn't shown hard evidence until they've made a working chip using 65nm ;)

Ohh, right. We'll play that game. So, this is an achievement (without showing or presenting anything!) but when STI actually presented the cells - that's not proof. Alrighty then. :rolleyes:

Also we're talking about logic here not eDRAM so the 20-30% eDRAM macro size advantage over NEC's is irrelevent with regards to Phillips/TMSC 65nm process capabilities. And if ATI's Xbox VPU doesn't have eDRAM then it's back to back irrelevent...

The embedded thing came to mind, but IBM has documented the transistor/logic density on their SOI sub-100nm processes. They have a plurality of papers on the logic, the density, power/thermal, physical size, speed, etc.

Philips showed nothing - nothing but talk, unlike the serious players like Intel, IBM. Talk is cheap. End of story.
 
Yes talk is cheap indeed...but I doubt Phillips/TMSC is just talking about making ICs uisng 65nm late 2004 early 2005 and never let it be realized.

And AFAIC CELL (4 GHz, 1 TFLOPS) also falls into the talk is cheap category ;)

I don't doubt it'll be made using a 65nm process though because by then everyone will have 65nm ICs anyway ;)
 
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