Well if we take Q1'15 and Q2'16 as the probable release dates, it would be 5 quarters, which is a bit more that the gap between the previous tegra chips afaik.
Why Q1 15 and a not a bit later? Unless we're picking at straws it makes little difference if between generations there are 11 or 13 months as just examples, it's more or less a yearly cadence.
If a company is concentrating mostly on markets like the automotive it doesn't really need any cut throat roadmap in the end either. Even K1 is far ahead compared to anything else automotive that it's already a joke to make any comparisons. In other words there's nothing wrong with it if things are slowing down, especially if Erista proves as efficient as everyone expects it to be.Though another thing is I see Erista sticking around for quite a while even after its 16nm succesor is released. 16nm capacity will be expensive and availability would be limited initially. There is no significant increase in density from 20nm to 16nm so the configurations would largely be similar. There would be some gains in power/and or performance, but at considerably higher production costs. So Erista may suffice for a lot of customers as it would be priced significantly lower and would not trail behind in performance all that much. So it could have a reasonably long life cycle.
The smaller the actual die estate of an SoC the higher the persentage of it those 5-6mm2 will be in the end. It's not the desktop market where you can still within boundaries throw around with transistors, area and burn a couple of watts more at worst.Agreed..but in this case it would be ~5-6 mm2 in total so its not all that high in the context of a ~100 mm2 SoC. And again I'll point you to my post above as to the reasons why I think it wont be completely useless. Given the timeframe, the features could very well be utilised towards the later part of its lifecycle.