NVIDIA Tegra Architecture

Here is what NVIDIA has said about the issue: "We believe they are caused by a material control issue during the production of a small number of tablets. This caused the material to become more brittle than expected. We are still in investigation mode and will continue to provide updates as we learn more. As previously stated, this imperfection appears to be cosmetic, so feel free to continue using your tablet".
 
When can Denver be expected in products ?

With twice the die size of an A15 core and more than twice the bandwidth, I don't think the performance is that impressive. But credit to Nvidia for trying something completely different.

Cheers
 
When can Denver be expected in products ?

With twice the die size of an A15 core and more than twice the bandwidth, I don't think the performance is that impressive. But credit to Nvidia for trying something completely different.

Cheers

i never get this die size argument, if your targeting the high end and you hit your performance targets ( perf/watt) then who cares you more then make up for it in your sell price. Caring about die size is for the other side of the curve while you race to the bottom......
 
When can Denver be expected in products ?

With twice the die size of an A15 core and more than twice the bandwidth, I don't think the performance is that impressive.

Then I guess you will also be unimpressed with the new QualComm 810 (Cortex A57) on 20nm as it is outperformed by Nvidia's Denver by 25%.

Cortex A57 at 20nm brings about a 45 percent improvement over Cortex A15 at 28nm in part because of the new process and in part because of the new ARMv8 instruction set, as you can see in the image below. However, Nvidia's Denver should be about 25 percent faster than that (80 percent faster than Cortex A15), even at 28nm.

http://www.tomshardware.com/news/qualcomm-snapdragon-smartphones-mobile-processor,27464.html
Also where exactly have you seen published factual (not speculative) die sizes on the K2 Tegra (Denver) and the K1 (Cortex A15)?

EDIT: The only data that I have found (and it is speculative) on the K1 die size is that it is 135 -- 140 square millimeters.

http://www.fool.com/investing/general/2014/06/04/just-how-big-is-nvidia-corporations-tegra-k1.aspx
 
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Then I guess you will also be unimpressed with the new QualComm 810 (Cortex A57) on 20nm as it is outperformed by Nvidia's Denver by 25%.

Also where exactly have you seen published factual (not speculative) die sizes on the K2 Tegra (Denver) and the K1 (Cortex A15)?

EDIT: The only data that I have found (and it is speculative) on the K1 die size is that it is 135 -- 140 square millimeters.

http://www.fool.com/investing/general/2014/06/04/just-how-big-is-nvidia-corporations-tegra-k1.aspx

Your performance data is just as speculative.
 
Current 32bit K1 is from what I've heard at 121mm2. Where the above speculation comes up with 135-140 is the author's own guess since not even a viable explanation how he comes up with that figure in that wannabe writeup.

Apart from that who says that 64bit K1 will be exactly the same size as the current 32bit K1 and not somewhat smaller? :rolleyes:
 
Apart from that who says that 64bit K1 will be exactly the same size as the current 32bit K1 and not somewhat smaller?

It should be smaller as it only has two Denver cores vs five Cortex A15 cores in the 32bit K1.

The original post questioning sizes was referring to the size of the Denver Core vs the Cortex A15 core and probably was referencing the artist rendered mock-up of the K1-32bit (Cortex A15) and the K1-64bit (Denver) which seems to imply that the Denver core is twice the size of the K1-32bit.


This mock-up should never have been used in determining any sizes period.

Unless Chipworks releases real die shots on the K1 (both A15 & Denver) we really won't know.
 
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Fair enough, but that doesn't make it any less speculative.

http://www.extremetech.com/computin...ass-performance-for-first-64-bit-android-chip

denver-64-bit-nvidia-core-performance-relative.jpg
 
Can you provide a link for this 121mm2?

I sure wish that Chipworks would do a full die shot analysis as that would end the speculation once and for all.

Why do things always pass by your noses? LOL :LOL:

http://forum.beyond3d.com/showpost.php?p=1855952&postcount=2485

As for the slide above what are a bunch of house own synthetic benchmark results supposed to tell anyone exactly? For one the wide majority of those applications have a quite questionable merit as CPU benchmarks and as a close second mind you we'd all prefer measurements from a more objective 3rd party and not NV's marketing rubbish.
 
Looks to be pure speculation with absolutely no data to back up the number.

Why don't you ask Rys yourself before you jump to any conclusions? At the very least he's an industry insider, as opposed to any wannabe speculatiing author around the internet you're much easier willing to quote as a "source".

Nonetheless a rough +50% increase compared to former Tegra SoCs isn't exactly a "small" bite.
 
Then I guess you will also be unimpressed with the new QualComm 810 (Cortex A57) on 20nm as it is outperformed by Nvidia's Denver by 25%.

Slideware vs slideware benchmarking leaves me even more unimpressed.

That's why I want to know when we can expect to see actual devices with Denver cores so we can run tests ourselves.

Also where exactly have you seen published factual (not speculative) die sizes on the K2 Tegra (Denver) and the K1 (Cortex A15)?

There was a slide in Nvidias own Denver presentation where four A15 cores for the 32bit version of the new Tegras was replaced by two Denver cores. Everything else was exactly the same.

Cheers
 
When can Denver be expected in products ?

With twice the die size of an A15 core and more than twice the bandwidth, I don't think the performance is that impressive. But credit to Nvidia for trying something completely different.

Cheers

The SoC die size, SoC mem. bandwidth, and SoC fab. process node are all expected to be the same between Tegra K1 32bit vs. Tegra K1 64-bit. So to achieve ~ 1.65x greater single core performance (measured in Geekbench) is pretty darn good all things considered. Anyway, the most important thing is that single-threaded CPU perf. per watt should go up significantly.

Note that the Cyclone CPU core in Apple's A7 SoC are also way larger than Cortex A15 core too (the Cyclone CPU core is probably much closer in die size to the Denver CPU core than it is to the A15 CPU core), and in some instances gets outperformed by the A15 core too:

65844.png


65845.png
 
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There was a slide in Nvidias own Denver presentation where four A15 cores for the 32bit version of the new Tegras was replaced by two Denver cores. Everything else was exactly the same.

That was an artistic conceptual diagram, not meant to represent die area.

Arguing about die area at this point is useless. Until nvidia discloses it or Chipworks takes a die photo, we have no useful data.
 
That was an artistic conceptual diagram, not meant to represent die area.

Arguing about die area at this point is useless. Until nvidia discloses it or Chipworks takes a die photo, we have no useful data.

They cut the number of cores from four to two. To me that indicates they hit die size or power consumption limitations.

But, you're right; It's all speculation at this point.

Cheers
 
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