Nvidia Pascal Speculation Thread

Discussion in 'Architecture and Products' started by DSC, Mar 25, 2014.

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  1. homerdog

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    Some CUDA dev misspoke when discussing HBM, saying it was integrated in the GPU die. Not worth mentioning really.
     
  2. CarstenS

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    To be fair, his talking point was Cuda and possible future optimizations, not the underlying hardware èn detail.
     
  3. sonen

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    TSMC's 16FF+ (FinFET Plus) technology can provide above 65 percent higher speed, around 2 times the density, or 70 percent less power than its 28HPM technology.
    http://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm

    Density improvement is pretty much mandatory, right?
    And you can have either 65% higher speed at the same power, or 70% less power at the same speed?
     
  4. MortLuzar

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    It is clear Nvidia wouldn't take the phone market by storm that late in the game no matter what.
    The phone market is huge, but nV's posibitites with or without the Phoenix platform weren't very different.
    But the platform helped bringing T4i to the market and it was an endeavor nV deemd worth taking.
    Even a 3-6 month difference in the automotive market right now could mark the difference between being just one small player holding a 10% of it or being the dominant market.
     
  5. Ext3h

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    No, it's not mandatory for the much smaller mobile GPUs where efficiency is rated higher than raw performance. That's why I'm suspecting, that the claimed efficiency numbers for Pascal are actually from an mobile GPU, not the high end one.

    And yes, you can only have either the one or the other, or at most a mixed calculation. Possibly with the option to have mixed transistor types on the same die.

    Plus, I'm not sure Nvidia or AMD are actually on FF+, but instead still on the original 16nm FF, where the possible gains in all 3 dimensions were only about half of what the improved proccess achieves.
     
  6. Ailuros

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    Does 16FF even exist anymore?
     
  7. Kaotik

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    Has anything been actually released yet on 16FF+? At least Apples chip is AFAIK 16FF, not 16FF+
     
  8. xpea

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    Huawei/HiSilicon Kirin 950 is on 16FF+
     
  9. Ailuros

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    Heh....thanks for that. I lived under the impression that A9 is actually 16FF+ *arghhhh*
     
  10. Blazkowicz

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    Apple has used the Samsung LPE process, as in "LP Early" (in addition to whichever 16FF it is)

    I would otherwise pester against Apple holding all the wafer orders, but the foundries have integrated that matter of fact and there's some benefit for everyone, though non Apple stuff is delayed.
     
  11. Ailuros

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    It's 16FF for A9 from what I can see on the internet. Usual writeups just mention 14nm Samsung and TSMC 16nm which doesn't help much. Anyway I think but am not sure that both NV's upcoming SoC and GPU chips are on 16FF+.
     
  12. Ext3h

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    Based on what? Tape-out was on 16FF. So unless they are developing a second revision right away, on different node, discarding the previous tape-out, I think it's unlikely that the first models are already going to be 16FF+. Neither for Polaris nor Pascal.

    Unless of course the delays from both vendors originate from the mutual decision to perform a second tape-out on 16FF+, in order not to risk being vastly undercut in terms of efficiency, respectively topped out in terms of performance by the competitor.
     
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  13. Kaotik

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    Source for tape-out being 16FF?
    Also, AMDs both Polaris chips are apparently GF/Samsung 14nm, not TSMC 16nm + or not.

    I haven't double checked, but has AMD actually ever said that any of their new GPUs would use TSMC? They have stated that "they" will use TSMC, but AMD has other products they could use TSMC for, too, like APUs
     
  14. Ext3h

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    Mixed things up for AMD, my fault. Even though there is most likely an equivalent of the improvements made on 16FF+ for GF 14nm.

    Why 16FF? The time frame. 16FF+ wasn't even announced back then, TSMC just started marketing 16FF with siginficantly worse characteristics.
     
  15. dbz

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    So are Xilinx's new MPSoC's ( Taped out back in July) so at least TSMC can boast a win over Intel+Altera on the 14/16nm FGPA front.
     
  16. Kaotik

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    It's called 14LPP, versus the 14LPE used by first chips like A9
     
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  17. Ailuros

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    And why should the timeframe argument stand for Polaris for 14LPP and not on the green side too for 16FF+. I don't insist, since "knowing" in my book is rather a strict first hand knowledge. According to background hearsay I was under the impression that Parker and Pascal are on 16FF+, AMD Polaris (both obviously) on 14LPP Samsung and Greenland/Vega10 or whatever they call it these days 16FF+. Either way anything 16FF sounds underwhelming. Here's what Hisilicon's marketing claimed for 28HPM vs. 16FF+ they've used for their Kirin950:

    http://images.anandtech.com/doci/9762/P1030606.jpg
    http://www.anandtech.com/show/9762/hisilicon-announces-kirin-950-huawei

    * No wonder neither/nor AMD or NVIDIA wanted to touch 20SoC.
    * If that's what 16FF+ can achieve in a best case scenario, it's the anything "less" that worries me for 16FF

    Also small tidbit from Andrei about the process:

    Since I'm now confused HiSilicon worked on 16FF+ improvements and Apple on 16FF improvements and they worked together how? Or are both Kirin950 and Apple A9 on 16FF+ after all?
     
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  18. Nebuchadnezzar

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    16FF was dropped.
     
  19. Ailuros

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    Thanks Nebu.

    ***edit: which isn't very encouraging for capacities. Is there any newsblurb/statement from TSMC how their capacities are projected for H2 this year?
     
    #799 Ailuros, Feb 25, 2016
    Last edited: Feb 25, 2016
  20. CarstenS

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    ... any post-earthquake statement...?
     
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