Nvidia Pascal Announcement

It sounds more like a refinement; I'd be very surprised though it doesn't add by at least 10% on a per cluster and per clock level compared to Maxwell.

 

Nvidia GP100 GPU architecture recap - full GPU has 3840 Shader processors

http://www.guru3d.com/news-story/nv...ecap-full-gpu-has-3840-shader-processors.html

 

What I said was the node was pushed further than ever before, the 600mm2 GPUs being proof of that. Previous node flagships would have stopped at the 780 Ti / 290X level, which would obviously be easier to beat on a new node.

 

40 to 28 is just one node, the old "half nodes" that used to exist. 28nm to 14nm is one full node (28 to 20) + FinFETs on the same 20nm BEOL rebranded to 14/16nm - basically more of a jump than 40 to 28 was but not two complete full node jumps like what Intel did from 32nm to 14nm.

 

I hope you find at least one to agree with all the above

 

Based on the Guru3D quote that pharma posted it seems they are continuing the Kepler -> Maxwell trend and going even lower on SPs/SM (64 vs 128) while keeping the register file size per SM the same. That alone should yield a nice efficiency bonus per SP (oh I'm sorry, CUDA Core™ ).

 

I do (hope so).

 

Nope, 32nm from TSMC, was cancelled if I remember correctly, and they jumped to 28nm, which is another full node drop.

28nm to 20nm is a full node jump, but 20nm just wasn't good enough because of leakage for performance chips. This is why TSMC went 16nm which employs smaller finfet transistors but keeps the layers similar to 20nm

 

https://en.wikipedia.org/wiki/Die_shrink

The 2nd part is basically what I said, TSMC's 16nm is 20nm with FinFET. Samsung's feature size is smaller. Overall it'll be slightly ahead of the 40nm to 28nm transition.

Yes TSMC's 32nm was cancelled, it caused AMD a hell of a problem with Cayman. TSMC used to do all the nodes, half and full, but they stopped doing that at 28nm. After that the numbers themselves just became meaningless.

 

55nm was the last node that followed the full/half cadence at TSMC.

40nm was smaller than the expected 45nm (a full node down from 65nm).

40nm became a new baseline, making 28nm a full node drop. It's not rocket science: the square root of 0.5*40*40 is 28.3.

 

It also features back-of-the-PCB portions 'shopped onto the front as well as provisions for GDDR5-Routing, i.e. blatantly fake, as does the subtext in the original say as well.

 

Pascal was meant to have less intrusive microarchitecture refinement, while the true goal was to quickly capitalise the new manufacturing process (make the largest possible die and stuff it to the edges) and introduce new features "on the periphery" of the ISA. Volta is where Nvidia is supposed to rework the internals.

 

Ah, so now you (re?)define pushing a process as making 600mm2 chips, like GP100?
So why did you write then that this time it should be more difficult when they've already done it?

Sometimes it seems that Adored is just a neural net trained phrase generator. The phrases sounds like real English, but there little real meaning to be found.

 

If you can't figure out that it's more difficult to beat Titan X on 16nm (with a midrange GPU) than it would be to beat the 780 Ti, it's your comprehension that's at fault.

What is so difficult about that? And FYI you're like a neural network sarcasm generator.

 

Hmm you can't say the 28nm was pushed more when there is a major architectural change from the 780ti to the Titan X. Both chips are quite large. And when the 780ti was launched on 28nm it might be have been hard to produce anything bigger without yields being sufficient for mass production without cutting out parts. We don't know this. Both AMD and NV had to drop DP units to create the 9xx and fury lines. What does that tell us? They couldn't push the process much further without redesigning their GPU's to accommodate the process.

 

That both AMD and NV could only fit part of their cancelled 20nm designs into 28nm chips?

 

no, 20nm chip wouldn't look anything like Maxwell2 or Fiji, they would have had so much more opportunity with transistor budgets, than dropping DP wouldn't have been their only option.

 

Along with the refinement to pre-emption and L2 Cache, occupancy.
Please could someone explain whether the atomic memory may have any benefit with "async compute" pertaining to data in gaming?
Cheers

 

My plan for this generation is to pick up GP106 for the living room and hold on to the desktop 780 Ti for a while longer and clear the Steam backlog. It's going to be hard to resist though. Big Volta probably won't hit retail till mid 2018.

 

Yeah and I'm betting even GP106 will beat a 780Ti, much less GP104.