Nvidia GT300 core: Speculation

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neliz said:
This is their official response, hardly breathtaking either.
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Just saying, anti-FUD FUD still is....

Proprietary standards punish gamers, not industry standards like DirectX11. Why is NVIDIA punishing gamers by putting in proprietary and closed standards like PhysX in games?
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Nice comeback :LOL:

he main reason for this is that NVIDIA normally send over an email asking if we've got samples and when we respond with a yes, we get some questions that they think we should be asking ourselves.
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See, it's just Nvidia being Nvidia....wouldn't matter if they were late to the party or not.
 
MfA said:
Because of the exponential relationship they can't give a flat percentage for that either Ailuros, still depends on design.

Does anyone know the average percentage of non redundant circuitry on a modern GPU so I can get some idea what 0.2 defect density will mean in October?

PS. that's per mm2 I assume? That seems awfully fucking high.
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Sorry don't know the average percents of redundant/non redundant circuitry on GPU. Saw some figures for 55nm on chiphell might be able to use them to take some guesses.

Looking at Digitimes article not sure they quite got it right(The week before they were talking of TSMC 40nm capacity increasing form 30k wafers per month to 40k wafers per month when that is actually the total 40nm volume expected for the quarter). They talked of 28nm trial runs in first half of 2010, but i think that is more the later half of 2010(at least for HK), maybe they meant 32nm?

I think that the defect density the 0.2 is per cm2, ie D0 = 0.2/cm^2
Substituting into:
Yield = (1 + A * D0/alpha) ^(-alpha)
Assuming alpha = 4 implies:
GT218 56mm2 => 89.5%
GT216 100mm2 => 82.2%
GT215 140mm2 => 76.6%
GT300 530mm2 => 39.9%

For the competition:
RV740 137mm2 => 76.7%
Juniper 180mm2 => 70.8%
Cypress 330mm2 => 54.3%

Above i guess gives you a rough starting point, obviously real life is much more complicated and need to take account of the relative redundancy levels in each design, should be fairly simliar for say GT218->GT215 and some sort of sliding scale across Evergreen series...need some real life figures to make further estimates.
 
trinibwoy said:
Just saying, anti-FUD FUD still is....



Nice comeback :LOL:



See, it's just Nvidia being Nvidia....wouldn't matter if they were late to the party or not.
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yeah.. just like the Red Sox got sick of "That's just Manny being Manny",.. at some point in time the consumer/market will answer back and I don't think nV will be able to keep "just being nVidia".
 
What market? You mean the few dozen people who care about Nvidia's "ethics"? :D It's product that matters man, and product alone. Nvidia's aggressive marketing is supported by the strength of their brand which was developed over years of producing good hardware. People will only get tired of them if they start producing crap.

For all the underdog cheerleading that happens in this industry, did that matter when Intel dropped Conroe, Penryn and Nehalem?
 
rjc said:
Sorry don't know the average percents of redundant/non redundant circuitry on GPU. Saw some figures for 55nm on chiphell might be able to use them to take some guesses.

Looking at Digitimes article not sure they quite got it right(The week before they were talking of TSMC 40nm capacity increasing form 30k wafers per month to 40k wafers per month when that is actually the total 40nm volume expected for the quarter). They talked of 28nm trial runs in first half of 2010, but i think that is more the later half of 2010(at least for HK), maybe they meant 32nm?

I think that the defect density the 0.2 is per cm2, ie D0 = 0.2/cm^2
Substituting into:
Yield = (1 + A * D0/alpha) ^(-alpha)
Assuming alpha = 4 implies:
GT218 56mm2 => 89.5%
GT216 100mm2 => 82.2%
GT215 140mm2 => 76.6%
GT300 530mm2 => 39.9%

For the competition:
RV740 137mm2 => 76.7%
Juniper 180mm2 => 70.8%
Cypress 330mm2 => 54.3%

Above i guess gives you a rough starting point, obviously real life is much more complicated and need to take account of the relative redundancy levels in each design, should be fairly simliar for say GT218->GT215 and some sort of sliding scale across Evergreen series...need some real life figures to make further estimates.
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Using those approximations, how many of each chip would you get on average per wafer? Can't remember how many of each fit per wafer though I'm sure it has been mentioned in this or R8xx-speculation thread.
 
Kaotik said:
Using those approximations, how many of each chip would you get on average per wafer? Can't remember how many of each fit per wafer though I'm sure it has been mentioned in this or R8xx-speculation thread.
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If your table napkin is running out of space you can simply divide the 300mm^2 wafer area by the chip area and round down a bit. Otherwise i suppose can use a calculator like here if you want to be more accurate.

The chiphell link previously mentioned is here it talks about ITRS2007 figures and i think the real life figures(though i might have stuffed up the translation again):
RV710 80mm^2 91%
RV730 140mm^2 84%
RV770 260mm^2 73%
GT200 450mm^2 57%
Not sure if above are simply calculated values of the author, the post mentions the TSMC 55nm process almost 10% above ITRS values.
 
when was the last the last time any saw sampsa stick out his neck :LOL: with presumable info, didn't he say something about the g80?
 
Razor1 said:
hmm when was the last time he didn't cards earlier then reviewer's ;)
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That's Engrish?

Anyway, reviewers won't get cards this month, probably not next either. Probably partners will get their first samples next month.
 
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