NV50 SPECS ???

[jlippone]

Those 32 vertex pipes would be nice.. 8)

 

[anaqer]

When will people ever learn that "nice" just doesn't cut it anymore?
They have to be - drumroll, please - extreme. Or at least radical.

 

[RussSchultz]

32 (24 real) pixels pipelines

Err...what should this mean? Eight imaginary pipelines?

integer only vs. floating point?

What are those eight for? Why not fp all the way? Don't quite get it...

iterators and things that don't need to be floating point, I presume.

 

[Ailuros]

People and their high hopes (goes for all 2005 releases)....

 

[2senile]

NV50 SPECS ???

I may get in trouble & even banned for revealing this but ........

...... there is a very good probability it will be ........


.... a graphics card!

 

[wireframe]

NV50 SPECS ???

I may get in trouble & even banned for revealing this but ........

...... there is a very good probability it will be ........


.... a graphics card!

Aha! So now we see that 2senile is an nVidia plant to spread misinformation. This is in the same line as ATi's "extreme pipelines". Nvidia is trying to leak the possibility that the NV50 is a video card when it is actually a bunch of bananas held together by duct tape.

Nice try nVidia, but I ain't crazy enough to swallow your lies when you make it that easy to spot the improbability of what you suggest!

/me goes back to looking at early montage shots of NV50
/me counts the bananas this monster will sport and wonders if they are extreme bananas. They look extreme...

 

[silence]

/me counts the bananas this monster will sport and wonders if they are extreme bananas. They look extreme...

just be carefull with what you do with those extreme bananas.

/me doesnt even wanna know

 

[martrox]

Somw of you really need to get out more............

 

[991060]

But if it has a big on-die cache, which can hold most of the intermediate result, thats another story(again, this is not quite possible, given the listed transistor count).

If you can't guarantee most of your intermediate results fit in this big cache..well..that cache (or local memory..) will not buy you (almost) nothing, performance wise.

Well, not all data a cpu needs resides in the cache when the program is running, but the cache does help a lot. And we all know what happens when NV3x run out of register resources, it's just another form of cache.

GPU is somewhat different architecture, it is much more latency tolerating, cache doesn't help GPU in the exact way it helps CPU. Given all these, I can still think out some interesting techniques which can make good use of on-die cache, cached shadow map and defered rendering are the first 2 hit my mind.

 

[nAo]

GPU is somewhat different architecture, it is much more latency tolerating, cache doesn't help GPU in the exact way it helps CPU. Given all these, I can still think out some interesting techniques which can make good use of on-die cache, cached shadow map and defered rendering are the first 2 hit my mind.

Maybe you're talking about a pool of fast local memory, not cache.
Anyway, in the end you just wrote about a couple of problems (shadow map, DR)
where you can garantee all your data will fit in cache/local memory

 

[cho]

what is the meaning of "UMI" ?

 

[Geo]

Somw of you really need to get out more............

I try, but the large muscly men in white coats won't let me!

 

[nVidia]

NV50 SPECS ???

I may get in trouble & even banned for revealing this but ........

...... there is a very good probability it will be ........


.... a graphics card!

Aha! So now we see that 2senile is an nVidia plant to spread misinformation. This is in the same line as ATi's "extreme pipelines". Nvidia is trying to leak the possibility that the NV50 is a video card when it is actually a bunch of bananas held together by duct tape.

Nice try nVidia, but I ain't crazy enough to swallow your lies when you make it that easy to spot the improbability of what you suggest!

/me goes back to looking at early montage shots of NV50
/me counts the bananas this monster will sport and wonders if they are extreme bananas. They look extreme...

He doesn't belong to us (just his cities ).

It won't be a gfx card, it'll be a gfx chip. The bestest one. And we will destroy ATI. ATI sux0rs. We will rule the world

 

[_xxx_]

what is the meaning of "UMI" ?

Unified memory interface?

 

[martrox]

nVidia ( the new poster, not the company), go away troll...this B3d, not Rage 3d of NV news.........

 

[Galduta]

NVIDIA 6900 Ultra XT 9000 HAL

http://www.neowin.net/forum/index.php?showtopic=284495&st=15

96 "Pipelines"
128 Texture Units
413 Arithmetic Logic Units (ALU)
981 Shader Operations per Cycle
4.2GHz Core
9134.7 Trillion Shader Operations per Second (at 4.2GHz)
512-bit 1024MB 2.9GHz GDDR7 Memory
921.6 TB/sec Bandwidth (at 2.9GHz)
1-3 hundred Transistors
1nm Manufacturing
Shader Model 14.0
NVIDIA SuperMemory
NVIDIA Omni Display Gadget (NODG)
Launch: Q3 2005
Performance: Over 200x Radeon 6800Ultras !!! (for single 69UXT9H)
32x Uber FSAA
FP64 blending, texturing
Programmable Primitive Processor/Tesselator
Advanced Artificial Intelligence
Optional Laser Beams

 

[Mummy]

[list of dreams]

you forgot the PCM..(programmable coffee maker)

 

[wireframe]

NVIDIA 6900 Ultra XT 9000 HAL

http://www.neowin.net/forum/index.php?showtopic=284495&st=15

96 "Pipelines"
128 Texture Units
413 Arithmetic Logic Units (ALU)
981 Shader Operations per Cycle
4.2GHz Core
9134.7 Trillion Shader Operations per Second (at 4.2GHz)
512-bit 1024MB 2.9GHz GDDR7 Memory
921.6 TB/sec Bandwidth (at 2.9GHz)
1-3 hundred Transistors
1nm Manufacturing
Shader Model 14.0
NVIDIA SuperMemory
NVIDIA Omni Display Gadget (NODG)
Launch: Q3 2005
Performance: Over 200x Radeon 6800Ultras !!! (for single 69UXT9H)
32x Uber FSAA
FP64 blending, texturing
Programmable Primitive Processor/Tesselator
Advanced Artificial Intelligence
Optional Laser Beams

Spot the typo...

 

[Killer-Kris]

Maybe you're talking about a pool of fast local memory, not cache.

Not to nitpick, but I thought that pretty much defined what cache is, especially the local part.

 

[MPI]

Maybe you're talking about a pool of fast <B>local</B> memory, not cache.

Not to nitpick, but I thought that pretty much defined what cache is, especially the local part.

No, a cache isn't addressable, they're supposed to be "transparent". Local memory(like for instance instruction reordering buffers, registers or whatever) aren't necessarily caches.