Configuring the hardware and performing operations as described above (e.g., configuring the CPU cores to run at different frequencies) may expose errors in synchronization logic, but if the real time behavior of the device is important, the timing testing mode itself may cause errors in operation, e.g., in the case of a video game console, errors due to the inability of the lower speed CPU cores to meet real time deadlines imposed by display timing, audio streamout or the like. According to aspects of the present disclosure, in timing testing mode, the device 300 may be run at higher than standard operating speed. By way of non-limiting example, the higher than standard operating speed may be about 5% to about 30% higher than the standard operating speed. By way of example, but not by way of limitation, in timing testing mode, the clock of the CPU, CPU caches, GPU, internal bus, and memory may be set to higher frequencies than the standard operating frequency (or the standard operating frequency range) of the device. As the mass produced version of the device 300 may be constructed in such a way as to preclude setting of clocks at above standard operating frequencies, specially designed hardware may need to be created, for example hardware that uses higher speed memory chips than a corresponding mass produced device, or uses the portion of a manufacturing run of a system on chip (SoC) that allows higher speed operation than average, or uses higher spec motherboards, power supplies, and cooling systems than are used on the mass produced device.
